The resulting timing error is output to a write clock compensator.
将所得定时误差输出到写时钟补偿器。
The compensator includes a phase rotator that controls which write clock phase is selected for output.
补偿器包括控制为输出选择哪个写时钟相位的相位旋转器。
The write clock is capable of generating equally spaced primary phases and phases intermediate the primary phases.
写时钟能够生成等间隔初相和初相中间的相位。
Kris called me at seven o 'clock last night, just as I was sitting down to write the Friday "Ask the Readers" post.
昨晚七点，我正准备坐下来写周五的“读者问答”帖子，克丽丝打来电话。
The design of CPLD has adopted the output clock of image sensor to write SDRAM.
CPLD电路设计采用图像传感器的输出时钟触发sdram写过程。
I write when I'm inspired, and I see to it that I'm inspired at nine o 'clock every morning.
我灵感来了才写作，不过我做到了让灵感每天上午九点钟来临。
I think I shouldn't abandon the habit of English diary. So write this to complement the vacant one which should be writed before 12 o 'clock.
我想我不应该放弃写英语日记的习惯。所以我写这篇来补上应该12点前写的文章的那个空。
The software design is finished, including system initialization, clock read and write, tracking Control, motor Drive module and so on.
同时完成了系统的软件设计，主要包括系统初始化，时钟读写，跟踪控制，电机驱动等。
The clock frequency is 1 MHz. The device samples sensor-read data during the write operation.
时钟频率为1兆赫。在写操作的过程中，设备从传感器独处的数据总取样。
Between chime and chime of the clock I can write essays by the score.
随着时钟一遍一遍的报时，我可以完成大量的文章。
This Design Idea describes how to implement a common clock (synchronous version) for an FPGA-based FIFO for data-width conversion with different-width read and write data ports.
本设计方案描述了为不同宽度读写数据端口的数据宽度转换，怎样基于FPGA的FIFO实现共有时钟(同步)。
The functions of the clock synchronization between nodes and parameters' read-write have been realized in the application design.
应用层的设计主要实现了节点间的时钟同步和参数的读写功能。
Once you verify the bus speed, you can confidently write the timer, serial-I/O, and other clock-dependent routines.
一旦检验总线速度，可以信赖的写定时器、串行I/O和其他时钟有关的程序。
During a WRITE operation, When this command is issued, data inputs can't be written with no clock delay.
在写操作中，如果该指令发出，输入数据马上无法写入。
Once you write the bus-clock-initialization routine, you may want to verify that the bus is running at the speed you intend before moving on to the rest of the project.
一旦写入总线时钟初始化程序，在继续工程其它部分之前，也许想检验总线是否以期望的速度运行。
I began to write from 8 0'clock without having breakfast.
早上8点，我还没有吃早餐就开始写了。
I began to write from 8 0'clock without having breakfast.
早上8点，我还没有吃早餐就开始写了。
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