Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
The factors that affect the interconnect wire delay and the resolution ways from to lower the signal swing and change switch threshold value aspect are described in this paper.
本文讨论了影响互连线延迟的因素，并讨论了从降低信号摆幅、改变开关阈值方面解决延迟、功耗等问题。
Key challenges on CMOS scaling down into nanometer regime are discussed, such as power supply and threshold voltage, short-channel effect, quantum effect, random doping distribution and wire delay.
本论文着重论述未来CMOS进入纳米尺寸的关键挑战，如：电源电压和阈值电压减小、短沟效应、量子效应、杂质数起伏以及互连线延迟等影响。
Mr Wire totted up the cost of supplying contraception to women who wished either to delay their childbearing years or to end them artificially but who were not using contraception.
MrWire计算了提供给那些想要推迟生育计划或者想要人工堕胎但是最终没能避孕女性的开销。
The principle and process of controlled cooling in highspeed wire production are introduced in simple, the process design thinking for delay controlled cooling analyzed.
简要介绍了高速线材控制冷却的原理与工艺要求，分析了延迟型控制冷却工艺的设计思路，该设计思路同时适用于大盘卷生产。
Due to the large load capacitance and increasingly serious inter-wire coupling, deep submicron buses are facing many problems like power, delay and reliability.
大的负载电容和日益严重的线间耦合使得深亚微米总线面临着功耗、延迟和可靠性等问题。
Experimental results show that our placement scheme achieves on average a total decrease of 27% in delay, 34% in wire-length and 42% in runtime, compared with the traditional placement methods.
实验结果表明，我们的布局算法与传统的布局算法相比，在时延上平均减少27%，在线长上平均减少34%，在运行时间上平均减少42%。
The two-wire serial interface enables outputs to be margined, tuned and ramped up and down at programmable slew rates with sequenced delay times.
两线串行接口，实现输出会被强制平仓，调整和上升和下降，在可编程的摆率与测序的延迟时间。 输入和输出电压，以及输入和输出电流和温度是可读的。
The two-wire serial interface enables outputs to be margined, tuned and ramped up and down at programmable slew rates with sequenced delay times.
两线串行接口，实现输出会被强制平仓，调整和上升和下降，在可编程的摆率与测序的延迟时间。 输入和输出电压，以及输入和输出电流和温度是可读的。
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