Based on the traditional placement methods at VLSI and system level, a novel model and algorithm of rapid system level placement for CDP is presented.
针对巨型机概念设计需求，在传统芯片级与系统级布局规划方法基础上，提出一种面向并行设计规划的快速布局模型与算法。
The VLSI testing is being pushed to the high-level based technology.
VLSI集成电路芯片测试技术正在向高层次测试推进。
The traditional magnitude comparator is based on gate-level techniques and not suitable for VLSI design.
传统的数字比较器采用门级设计技术，电路结构不规则，不利于大规模集成电路的设计。
According to the requirement of the VLSI and the wide application of power electronics, IP soft core of SPWM generation system is designed. And it can be widely applied in system level chip design.
论文针对目前大规模集成电路设计要求，结合电力电子应用，设计了一个SPWM信号产生系统IP软核，该软核可广泛应用于系统级芯片设计中。
All of these not only sum up the system-level test technique of VLSI, But also have a great significance for improving the testability of VLSI.
该研究和设计不仅对复杂电子设备系统级测试技术进行了总结，而且对改善电子设备系统级测试性能具有十分重要的指导意义。
All of these not only sum up the system-level test technique of VLSI, But also have a great significance for improving the testability of VLSI.
该研究和设计不仅对复杂电子设备系统级测试技术进行了总结，而且对改善电子设备系统级测试性能具有十分重要的指导意义。
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