VLSI layout circuit extraction provides a reliable tool for the estimation of circuit's performance.
集成电路版图提取为精确估计电路性能提供了可靠的手段。
In this dissertation, we designed the architecture and the workflow of the analog VLSI layout automation tool.
本文设计了模拟集成电路版图设计自动化工具的流程。
The placement problem is an important problem in VLSI layout design, but results from traditional methods are not satisfied.
布局问题是VLSI布图设计中的重要问题，传统的方法很难得到满意的解答。
The basic theory of resistance extraction in VLSI layout verification is described. A novel resistance extractor based on the boundary element method is presented.
介绍了VLSI版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。
The result shows that it is more simple, regular in layout and faster than the traditional one. It is suitable for the design of VLSI, and has some study and impractical value.
研究表明，和传统的数字比较器相比，这种电路具有结构简单，布局规则，运算速度快等优点，适用于大规模集成数字比较器的设计，具有一定的研究和实用价值。
The algorithm has also been employed as a program block in our VLSI building block layout system which has been developing.
算法已作为正在研充的VLSI积木块布图设计系统中的一个模块。
Two-layer channel routing is one of the key steps in the automatic layout design of VLSI chips.
两层通道布线问题在超大规模集成电路自动布图设计中是关键步骤之一。
It is important to the calculation of VLSI critical area and the optimization of IC layout design.
这对计算VL SI关键面积、指导版图优化设计和提高IC成品率有重要意义。
Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI.
提出基于划分的逻辑图布图策略，有效解决超大规模集成电路(VL SI)逻辑原理图自动生成中规模与速度的矛盾，给出详细的划分模型。
Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI.
提出基于划分的逻辑图布图策略，有效解决超大规模集成电路(VL SI)逻辑原理图自动生成中规模与速度的矛盾，给出详细的划分模型。
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