VLSI partitioning is an effective method for reducing complexity of VLSI circuit design.
电路划分是降低超大规模集成电路设计复杂性的有效方法。
This paper proposes a new algorithm for computing the maximum distance sequence, which are general for VLSI circuit test and software test technique.
本文提出了求多个测试序列极大距离的算法，该算法对数字电路的测试和软件测试技术是通用的。
This study offers a theoretical basis and noise detection method for VLSI circuit components selection, faults diagnosis and localization, and reliability analysis.
这一研究将为VLSI电路器件的严格筛选、故障诊断及定位、VLSI电路的可靠性研究提供新的理论依据和检测方法。
The method utilizes the estimation of time-related power consumption of the signal in the VLSI circuit and system design to conquer the restriction of the prior method.
本发明方法能够在VLSI电路和系统设计中，信号在时间上相关性 时的估计功耗，克服了原有方法的局限性。
Facing the challenge of design scale of VLSI becoming larger, except for circuit parallel, the existing basic parallel approaches cannot solve test generation complexity problems radically.
面对VLSI设计规模日益增大的挑战，除了电路并行以外，其它已有的基本并行策略都无法从根本上解决测试生成的复杂性问题。
Very large-scale integration (VLSI) vastly increased circuit density, giving RisE to the microprocessor.
大规模集成电路更大的增加了微处理器的电路密度。
From the introduction of design process of every module circuit, we can see easily some general feature of VLSI design with HDL.
通过对各个模块设计过程的介绍，阐明了使用HDL语言设计超大规模集成电路的一般特点。
This paper theoretically advances the conception of reverse statistical simulation in the statistical analysis of VLSI, by which a statistical simulator of NMAS digital circuit STANMOS is developed.
本文在理论上提出了逆向统计模拟思想，并用以开发了NMOS数字集成电路统计模拟通用软件——STANMOS。
VLSI layout circuit extraction provides a reliable tool for the estimation of circuit's performance.
集成电路版图提取为精确估计电路性能提供了可靠的手段。
Testing is an important process for industrial production of VLSI chips, the goal of which is to detect circuit faults caused by manufacturing process.
测试是芯片产品规模化生产的重要环节，其目标是检测制造工艺过程引起的电路故障。
From the introduction of design process of every module circuit, we can see easily some general feature of VLSI design with HDL. methodology.
通过对各个模块设计过程的介绍，阐明了使用HDL语言设计超大规模集成电路的一般特点。
As the scale of digital circuits become very bigger and the function of circuit become very complicated recently, it is difficult to ensure the correctness of design in VLSI system.
近年来，由于电路规模不断增大和电路功能日趋复杂，使得大规模集成电路的设计很难保证逻辑设计的正确无误。
So the efficient verification of the design and implement of circuit must be introduced for building the higher responsible VLSI system.
为了设计和建立高可靠性的VLSI系统，必须对VLSI的设计和实现进行有效的验证。
At last, typical circuits and circuit techniques applied to telecommunication LSI/VLSI are provided.
并通过实例说明通信LSI/VLSI中典型的电路和技术。
VLSI IC's are used to implement different parts of a circuit, connections between individual circuits are built using the pins on the IC's connected to one another with a printed circuit board.
大量的小型集成、中型集成电路、大规模集成电路和超大规模的集成电路被用在大规模电路的各个部分，这些电路被分别固定在相连的电路板上。
VLSI IC's are used to implement different parts of a circuit, connections between individual circuits are built using the pins on the IC's connected to one another with a printed circuit board.
大量的小型集成、中型集成电路、大规模集成电路和超大规模的集成电路被用在大规模电路的各个部分，这些电路被分别固定在相连的电路板上。
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