• So this paper focuses on Convolutional code and Viterbi decoding algorithm.

    论文主要讨论卷积码编码维特比译码算法。

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  • Viterbi decoding techniques that include multi-stage Viterbi decoding of encoded signals.

    包括编码信号进行多级维特解码维特比解码技术

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  • The decoding execution unit executes Viterbi decoding, and it includes an ACS processing unit with a variable radix.

    穿孔单元解穿孔该穿孔的卷积序列,然后,将结果输出解码执行单元。

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  • In this paper, convolution code is carried out by the structure of coder, and decoding is carried out by Viterbi decoding algorithm.

    本论文中根据编码器关系实现卷积编码,维特译码算法实现卷积码的解码

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  • The states of Viterbi decoding were reduced through the state combination. The signal was detected combined with the decision feedback.

    序列检测阶段通过状态融合减少维特比译码状态数,然后结合判决反馈进行检测。

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  • As an example, we calculate the Euclidean distance spectrum of error paths under viterbi decoding and BER upper bound for four-state Trellis-coded 8 PSK.

    以四状态网格编码8PS K系统计算维特比译码时错误路径欧氏距离及由此得到的误比特上限

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  • In this paper, a reduced-state trellis for M-ary CPFSK is presented under the condition that the MSED is not reduced therefore the complexity of Viterbi decoding is reduced.

    本文减少最小平方欧氏距离前提提出多进制CPFSK的减少状态格状图,从而减少了维特比译码复杂度

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  • Viterbi decoding is discussed and the performances of convolutional encoding and Viterbi decoding are analyzed by computer simulation, and compared to other decoding methods.

    对不同码率、约束长度卷积译码系统误码性能进行计算机仿真其他译码方案的性能进行了比较

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  • Viterbi algorithm is a kind of maximum likelihood decoding method, which can obtain high decoding speed and cost fixed decoding time, so it is widely used in deep space communication.

    维特比译码算法最大似然译码可以得到较高的译码速度以及译码计算时间固定因而通信中得到广泛应用。

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  • At the same time, the thesis research the convolution coding and decoding theory in detail, as well as present the process of research on theory and simulation of this viterbi decoder.

    同时文章卷积译码理论方法进行了较为细致研究给出此设计方案的理论仿真分析。

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  • This paper introduces a method of hardware implementation in channel decoding, giving an emphasis on the decoding of punctured code and synchronization module following Viterbi decoder.

    文中提出了信道译码硬件实现方案,解决了其中删节解码Viterbi译码同步等难题。

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  • VITERBI decoder use truncate decoding which increases the decoding efficiency with little influence on decoding accuracy.

    Viterbi译码采用译码几乎不影响译码准确度的基础大大提高解码效率

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  • The stage reduction unit (80) USES the additional information to limit the decoding by the Viterbi decoder (81) to certain subsequent stages.

    减阶单元(80)使用附加信息维特比译码器(81)进行译码限制特定后续阶。

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  • The constrained Viterbi algorithm (C-VA) makes use of the right decoding results to improve the conventional Viterbi algorithm.

    约束维特算法利用已知正确信息,对维特比算法进行改进

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  • The constrained Viterbi algorithm (C-VA) makes use of the right decoding results to improve the conventional Viterbi algorithm.

    约束维特算法利用已知正确信息,对维特比算法进行改进

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