The Viterbi decoder (81) decodes the received symbols (50) by means of a modified Viterbi algorithm.
维特比译码器（81）通过更改后的维特比算法对接收符号（50）进行译码。
The performance can be improved greatly by using the channel state information (CSI) in Viterbi decoder.
在维特比译码器译码时，应用信道状态信息(CSI)，可以明显提高系统性能。
VITERBI decoder use truncate decoding which increases the decoding efficiency with little influence on decoding accuracy.
Viterbi译码器采用截尾译码，在几乎不影响译码准确度的基础上大大提高了解码效率。
The stage reduction unit (80) USES the additional information to limit the decoding by the Viterbi decoder (81) to certain subsequent stages.
减阶单元(80)使用该附加信息将维特比译码器(81)进行的译码限制为特定的后续阶。
This Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoders using traditional trace-back methods.
与采用传统回溯法的译码器相比，该译码器具有较低的译码时延、有效的存储空间管理和较低的硬件复杂度。
At the same time, the thesis research the convolution coding and decoding theory in detail, as well as present the process of research on theory and simulation of this viterbi decoder.
同时，文章对卷积编译码的理论和方法进行了较为细致的研究，并给出此设计方案的理论仿真分析。
This paper introduces a method of hardware implementation in channel decoding, giving an emphasis on the decoding of punctured code and synchronization module following Viterbi decoder.
文中提出了信道译码硬件实现的一种方案，解决了其中删节码的解码和Viterbi译码后同步等难题。
This paper introduces a method of hardware implementation in channel decoding, giving an emphasis on the decoding of punctured code and synchronization module following Viterbi decoder.
文中提出了信道译码硬件实现的一种方案，解决了其中删节码的解码和Viterbi译码后同步等难题。
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