As an example, we calculate the Euclidean distance spectrum of error paths under viterbi decoding and BER upper bound for four-state Trellis-coded 8 PSK.
以四状态网格编码8PS K系统为例，计算了维特比译码时错误路径的欧氏距离谱及由此得到的误比特率上限。
So this paper focuses on Convolutional code and Viterbi decoding algorithm.
本论文主要讨论卷积码编码与维特比译码算法。
Viterbi algorithm is the most likelihood decode algorithm of convolution code.
维特比译码算法是卷积编码的最大似然译码算法。
CPM modulation linear equalizer, the use of Viterbi browser sentencing verdict.
CPM调制的线性均衡器，使用维特比判决器进行判决。
Viterbi decoding techniques that include multi-stage Viterbi decoding of encoded signals.
包括对编码信号进行多级维特比解码的维特比解码技术。
The Viterbi decoder (81) decodes the received symbols (50) by means of a modified Viterbi algorithm.
维特比译码器（81）通过更改后的维特比算法对接收符号（50）进行译码。
The performance can be improved greatly by using the channel state information (CSI) in Viterbi decoder.
在维特比译码器译码时，应用信道状态信息(CSI)，可以明显提高系统性能。
VITERBI decoder use truncate decoding which increases the decoding efficiency with little influence on decoding accuracy.
Viterbi译码器采用截尾译码，在几乎不影响译码准确度的基础上大大提高了解码效率。
These modules were comprised of the realization of FEC and the decode of Viterbi, the shape of base-band wave, FFT and so on.
这些关键模块包括基带系统中的差错控制编码和维特比译码，成形滤波，FFT变换等。
The constrained Viterbi algorithm (C-VA) makes use of the right decoding results to improve the conventional Viterbi algorithm.
约束维特比算法是利用已知的正确信息，对维特比算法进行改进。
In this paper, convolution code is carried out by the structure of coder, and decoding is carried out by Viterbi decoding algorithm.
在本论文中，根据编码器的关系实现卷积码的编码，用维特比译码算法实现卷积码的解码。
The states of Viterbi decoding were reduced through the state combination. The signal was detected combined with the decision feedback.
在序列检测阶段通过状态融合减少维特比译码的状态数，然后结合判决反馈进行检测。
The stage reduction unit (80) USES the additional information to limit the decoding by the Viterbi decoder (81) to certain subsequent stages.
减阶单元(80)使用该附加信息将维特比译码器(81)进行的译码限制为特定的后续阶。
For each data symbol and each combined state, a Viterbi processor (703) determines a path metric and a substate indication for each path to the combined state.
对于每个数据码元和每个组合的状态，维特比处理器（703）确定对于到组 合状态的每个路径的路径度量和子状态指示。
This Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoders using traditional trace-back methods.
与采用传统回溯法的译码器相比，该译码器具有较低的译码时延、有效的存储空间管理和较低的硬件复杂度。
In this paper, a reduced-state trellis for M-ary CPFSK is presented under the condition that the MSED is not reduced therefore the complexity of Viterbi decoding is reduced.
本文在不减少其最小平方欧氏距离的前提下，提出了多进制CPFSK的减少状态格状图，从而减少了维特比的译码复杂度。
Viterbi decoding is discussed and the performances of convolutional encoding and Viterbi decoding are analyzed by computer simulation, and compared to other decoding methods.
对不同码率、约束长度的卷积码编译码系统的误码性能进行了计算机仿真，并与其他译码方案的性能进行了比较。
Viterbi algorithm is a kind of maximum likelihood decoding method, which can obtain high decoding speed and cost fixed decoding time, so it is widely used in deep space communication.
维特比译码算法是一种最大似然译码，它可以得到较高的译码速度以及译码计算时间固定，因而在深空通信中得到广泛应用。
A path selection processor (709) of the Viterbi processor (703) selects a selected path and a selected substate indication for the path which corresponds to a highest likelihood path metric.
维特比处理器(703)的路径选择处理器(709)选择相应于最高似然路径度量的被选择路径和被选择子状态指示。
The Maximum Likelihood Sequence Estimation (MLSE) using the Viterbi Algorithm (VA) is commonly recommended for the equalization, which can only accommodate the channels with limited time delay spread.
常用的最大似然序列估计(MLSE)均衡器采用维特比算法(VA)，它只能用于具有较小时延扩展的信道。
The Maximum Likelihood Sequence Estimation (MLSE) using the Viterbi Algorithm (VA) is commonly recommended for the equalization, which can only accommodate the channels with limited time delay spread.
常用的最大似然序列估计(MLSE)均衡器采用维特比算法(VA)，它只能用于具有较小时延扩展的信道。
应用推荐