The VHDL design organization and data types are described. Applications of VHDL to VLSI design are discussed.
概要地介绍了VHDL的设计组织和数据类型，并对VHDL的特点及其在VLSI设计中的应用要点做了一些探讨。
There are four parts about the digital transmitter design: scheme selection, system design, hardware design and VHDL design.
数字发射机设计主要包括方案选择、系统设计、硬件电路实现及VHDL设计四个部分。
Finally, it gives an example that the VHDL design was used in airborne equipment successfully and the advantages brought with it.
最后，给出了一个成功应用VHDL设计的机载设备及其带来的优点。
A solution for property verification of synchronous VHDL design is introduced, and VERIS an efficient symbolic model checker is implemented.
介绍了一个针对同步时序电路VHDL设计的性质验证的解决方案——一个有效的符号模型判别器veris。
Through a simple and complete and typical 12-band counter VHDL design examples, to make preliminary understanding of VHDL expression and the resulting VHDL language phenomenon and statement rules.
通过一个简单完整而典型的12进制计数器的VHDL设计实例，来使大家初步了解用VHDL表达以及由此而引出的VHDL语言现象和语句规则。
This paper deals design method of digital system of top-down, VHDL and applications of in technology ASIC.
本文论述了数字系统自顶向下的设计方法、VHDL及其在ASIC技术中的应用。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The design of source files by VHDL, compilation and synthesis, and implementation methods with HDPLD are discussed.
着重讨论了用VHDL设计源文件，通过综合编译，用HDPLD实现的方法。
This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.
介绍了VHDL逻辑级模拟系统中模拟模块的设计和实现。
We take the Full Adder as an example to introduce the use of VHDL in the design of digital system, the experiment of digital circuit and the teaching.
本文以全加器为例介绍其在数字系统设计和数字电路实验及教学中的应用。
This article studied how to design a counter based on VHDL which will be applied in drip-irrigation controller.
本文针对VHDL在滴灌控制器的定时器芯片的设计展开研究。
Lastly, the hardware circuit, VHDL program design and debugging methods based on FPGA are discussed.
最后对基于现场可编程门阵列(FPGA)的硬件电路、VHDL语言程序设计及调试方法进行了讨论。
With the analysis of the experimental outcome, this article introduces the superiority of VHDL in the digital circuit design.
通过对设计结果的分析，阐述了VHDL在数字电路设计中的优越性。
This paper presents advantage of M-sequences ciphers system by using m sequences as key sequences and proposes the design method of this system based on VHDL language.
文章介绍了用M序列为密钥序列的序列密码系统的优越性，提出了采用VHDL语言来设计这种序列密码系统的新方法。
The soft core can adopt interpolation technique to process image, can make use of VHDL to design FPGA, and can also use wavelet transform to improve the arithmetic of image process.
该软核采用插值算法进行图像处理，利用硬件编程语言VHDL对FPGA进行设计，也可利用小波变换方法对图像处理算法进一步优化。
The whole design is described in VHDL. By logic optimization, the controller has an advantage of less resource utilization and less clock delay compared with other similar controllers.
整个设计采用VHDL语言描述，经过逻辑优化，该显示控制器有着比同类控制器占用资源少、时钟延迟小等优点。
VHDL, however, can make effective description of the digital system and enable logical synthesis to produce high design density.
VHDL语言能方便地进行数字系统描述，而且能使逻辑综合产生更大的设计密度。
VHDL can provide high level language structure, describe large scale circuit conveniently and complete design rapidly.
VHDL能提供高级语言结构，方便地描述大型电路，快速地完成设计。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
VHDL language is the important tool of electronic design, and data object is one of essential language factors.
VHDL语言是现代电子设计的重要工具，数据对象是其中的重要语言要素。
VHDL is very suitable to the design of programmable logic devices.
VHDL非常适用于可编程逻辑器件的应用设计。
A general method of intelligent controller design and closed-loop test based on VHDL and FPGA implementation is proposed.
提出了一种基于VHDL描述、FPGA实现的智能控制器设计和闭环测试的一般性方法。
Based on a classical example, we specify how. to begin a Top -down design with VHDL. Also, we point out that how to incorporate VHDL into a being used EDA environment.
结合一个典型例子，说明如何采用VHDL开始一个自顶向下的设计，指出如何在现有的环境中有效开发VHDL的应用。
Complex program logic device (CPLD) has been chosen as the hardware design platform, driving schedule generator has been described with VHDL.
选用复杂可编程器件(CPLD)作为硬件设计载体，使用VHDL语言对驱动时序发生器进行了硬件描述。
VHDL is a necessary tool in the area of EDA circuit design.
VHDL是EDA领域中电路设计必不可少的工具。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。
An alarm system for security guarding designed with FPGA is discussed in this thesis, and the theory and structure as wall as the design for VHDL module are also given bellow.
文中讨论利用FPGA设计的用于安全防范的报警系统，讲述系统的原理与结构，给出VHDL的模块设计。
Nowadays, FPGA and VHDL are two important tools in embedded system design.
F PGA和V HDL是当今嵌入式系统设计的两个重要工具。
By using VHDL as design language and according to the principle of VGA, a controller of VGA display system based on FPGA is designed.
依据VGA显示原理，利用VHDL作为设计语言，设计了一种基于现场可编程器件FPGA的VGA多图像控制器，并在硬件平台上实现设计目标。
Through design examples, this paper introduces the method of digital systems design based on VHDL.
通过设计实例，介绍了利用VHDL语言进行数字系统设计的方法。
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