The lexers for case-insensitive languages like Pascal and VHDL are slightly more complicated because they must parse, for example, begin and begin and generate the same token for the parser.
Pascal和VHDL等大小写敏感语言中的lexer要复杂一些，因为它们必须解析begin和begin等内容并为解析器生成相同的标记。
VHDL hardware description language based, a very good book, time to take a look!
VHDL硬件描述语言基础，非常好的一本书，有时间不妨看看！
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
The serial communication interface chip design was realized by application of schematic diagram and VHDL language.
采用自顶向下的设计方法，用原理图和VHDL语言这两种输入对串行通信接口芯片进行设计。
Having analyzed the difference of the two languages, this paper provides a method of translating C language into VHDL language, and the method is implemented.
文章通过分析两种语言的区别，提出并实现了适于表达C语言描述内容的VHDL结构形式，并对几种C语言结构提出合理的转换方案。
The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
Lastly, the hardware circuit, VHDL program design and debugging methods based on FPGA are discussed.
最后对基于现场可编程门阵列(FPGA)的硬件电路、VHDL语言程序设计及调试方法进行了讨论。
In this paper, the VHDL high level abstract model is outlined, and the language basics in VHDL which can be used to support and represent this model are introduced.
本文概述了VHDL的高级抽象模型，并对VHDL中支持和表示此模型的语言基础作了简介。
The program is compiled with VHDL(hardware description language).
试验程序由VHDL硬件描述语言编写。
So it has distinctive meaning to make VHDL as the input language in high-level synthesis, because it can combine the virtue of it as industry standard and high-level synthesis itself.
因此将VHDL语言作为高级综合的输入描述可以把它作为工业标准的优点与高级综合的自身优点结合起来，其意义十分明显。
The logic synthesis of VHDL language is a method that the description of higher abstract hierarchy is shifted to lower one automatically.
VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。
Through design examples, this paper introduces the method of digital systems design based on VHDL.
通过设计实例，介绍了利用VHDL语言进行数字系统设计的方法。
This paper presents advantage of M-sequences ciphers system by using m sequences as key sequences and proposes the design method of this system based on VHDL language.
文章介绍了用M序列为密钥序列的序列密码系统的优越性，提出了采用VHDL语言来设计这种序列密码系统的新方法。
The paper studies the hardware of the interface circuit and how to control the sweep fingerprint sensor to complete the task of high quality fingerprint gathering with hardware language VHDL.
重点研究接口电路的硬件组成和如何采用硬件语言VHDL编程控制滑动式指纹传感器以完成高质量的指纹采集工作。
Then data gained by simulation through the hardware language VHDL were listed out, which proved the validity of the conversion on hardware system.
并列出了一组由VHDL硬件语言模拟得到的转化结果的数据，来证实能在硬件上转化的正确性；
Aiming at the design problem of traffic light controller, this paper puts forward a hardware realization method of traffic light controller with VHDL.
针对交通信号灯控制器的设计问题，提出了基于VHDL语言的交通信号灯控制器的硬件实现方法。
In this paper, a kind of chip of video complex black signal is described with VHDL.
采用VHDL硬件描述语言设计一种再生视频复合消隐信号的专用芯片。
On the base of analyzing the structure and the design difficulty of the asymmetric synchronous FIFO, an asymmetric synchronous FIFO is achieved by using VHDL language and FPGA in this paper.
本文在分析了非对称同步fifo的结构特点及其设计难点的基础上，采用VHDL描述语言，并结合FPGA，实现了一种非对称同步fifo的设计。
Summarized the concurrent statements and sequential statements of VHDL language, and described their types and the characteristic.
简单概述了VHDL语言的并行语句和顺序语句，描述了其种类和特点。
The soft core can adopt interpolation technique to process image, can make use of VHDL to design FPGA, and can also use wavelet transform to improve the arithmetic of image process.
该软核采用插值算法进行图像处理，利用硬件编程语言VHDL对FPGA进行设计，也可利用小波变换方法对图像处理算法进一步优化。
The whole design is described in VHDL. By logic optimization, the controller has an advantage of less resource utilization and less clock delay compared with other similar controllers.
整个设计采用VHDL语言描述，经过逻辑优化，该显示控制器有着比同类控制器占用资源少、时钟延迟小等优点。
VHDL, however, can make effective description of the digital system and enable logical synthesis to produce high design density.
VHDL语言能方便地进行数字系统描述，而且能使逻辑综合产生更大的设计密度。
VHDL can provide high level language structure, describe large scale circuit conveniently and complete design rapidly.
VHDL能提供高级语言结构，方便地描述大型电路，快速地完成设计。
VHDL language is the important tool of electronic design, and data object is one of essential language factors.
VHDL语言是现代电子设计的重要工具，数据对象是其中的重要语言要素。
Based on FPGA the equipment with the functions of asynchronous serial data transfer, self-test capability, fuze product test and so on is designed and realized by VHDL program.
该设备以FPGA为核心，使用VHDL硬件描述语言设计并实现了异步串行通讯、测试设备的自检、引信产品的检测等几大功能。
VHDL is considered as a core of digital system design and a key technique of implement digital systems design.
硬件描述语言(VHDL)是数字系统高层设计的核心，是实现数字系统设计新方法的关键技术之一。
The 28 bit plus-minus counter was realized in VHDL.
用VHDL语言设计实现了28位加减计数器。
Variable presents a specific feature of VHDL sequential statements.
变量是VHDL 语言中顺序语句的一个特征。
The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language.
本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。
应用推荐