The VHDL simulator, which implements the behavioral semantics of VHDL descriptions, is one of the most basic components of a VHDL-based EDA environment.
VHDL模拟器是基于VHDL的EDA环境的最基本的组成部分，它所实现的是VHDL描述的行为语义。
The lexers for case-insensitive languages like Pascal and VHDL are slightly more complicated because they must parse, for example, begin and begin and generate the same token for the parser.
Pascal和VHDL等大小写敏感语言中的lexer要复杂一些，因为它们必须解析begin和begin等内容并为解析器生成相同的标记。
This paper deals design method of digital system of top-down, VHDL and applications of in technology ASIC.
本文论述了数字系统自顶向下的设计方法、VHDL及其在ASIC技术中的应用。
The methods to solve several problems of designing VHDL synthesis system are given in this paper.
讨论了在研究和设计VHDL综合系统时遇到的若干问题的解决方案。
VHDL hardware description language based, a very good book, time to take a look!
VHDL硬件描述语言基础，非常好的一本书，有时间不妨看看！
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The design of source files by VHDL, compilation and synthesis, and implementation methods with HDPLD are discussed.
着重讨论了用VHDL设计源文件，通过综合编译，用HDPLD实现的方法。
At last, this thesis realizes digital down converter based on FPGA, and the whole designing process includes algorithm simulation, VHDL description, FPGA simulation and real system test.
最后，基于FPGA对数字下变频进行了设计及实现，具体包括：算法仿真、VHDL描述、FPGA仿真和实际系统测试。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
With the analysis of the experimental outcome, this article introduces the superiority of VHDL in the digital circuit design.
通过对设计结果的分析，阐述了VHDL在数字电路设计中的优越性。
This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.
介绍了VHDL逻辑级模拟系统中模拟模块的设计和实现。
The serial communication interface chip design was realized by application of schematic diagram and VHDL language.
采用自顶向下的设计方法，用原理图和VHDL语言这两种输入对串行通信接口芯片进行设计。
This article studied how to design a counter based on VHDL which will be applied in drip-irrigation controller.
本文针对VHDL在滴灌控制器的定时器芯片的设计展开研究。
Having analyzed the difference of the two languages, this paper provides a method of translating C language into VHDL language, and the method is implemented.
文章通过分析两种语言的区别，提出并实现了适于表达C语言描述内容的VHDL结构形式，并对几种C语言结构提出合理的转换方案。
We take the Full Adder as an example to introduce the use of VHDL in the design of digital system, the experiment of digital circuit and the teaching.
本文以全加器为例介绍其在数字系统设计和数字电路实验及教学中的应用。
The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
Lastly, the hardware circuit, VHDL program design and debugging methods based on FPGA are discussed.
最后对基于现场可编程门阵列(FPGA)的硬件电路、VHDL语言程序设计及调试方法进行了讨论。
In this paper, the VHDL high level abstract model is outlined, and the language basics in VHDL which can be used to support and represent this model are introduced.
本文概述了VHDL的高级抽象模型，并对VHDL中支持和表示此模型的语言基础作了简介。
The program is compiled with VHDL(hardware description language).
试验程序由VHDL硬件描述语言编写。
This paper presents advantage of M-sequences ciphers system by using m sequences as key sequences and proposes the design method of this system based on VHDL language.
文章介绍了用M序列为密钥序列的序列密码系统的优越性，提出了采用VHDL语言来设计这种序列密码系统的新方法。
The logic synthesis of VHDL language is a method that the description of higher abstract hierarchy is shifted to lower one automatically.
VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。
A general method of intelligent controller design and closed-loop test based on VHDL and FPGA implementation is proposed.
提出了一种基于VHDL描述、FPGA实现的智能控制器设计和闭环测试的一般性方法。
Through design examples, this paper introduces the method of digital systems design based on VHDL.
通过设计实例，介绍了利用VHDL语言进行数字系统设计的方法。
The circuit design of serial synchronous communication based on VHDL includes design of serial synchronous sending circuit and receiving circuit.
基于VHDL的串行同步通信电路设计，包括串行同步发送电路和接收电路的设计。
VHDL silicon compiler is a supplementary tool of the IC CAD system-XUECAD. The algorithms of modified VHDL silicon compilers placing and routing are introduced in this paper.
VHDL硅编译器是XUECAD集成电路自动设计系统的一个辅助工具。本文将着重介绍改进后的VHDL硅编译器的布局、布线算法。
The 28 bit plus-minus counter was realized in VHDL.
用VHDL语言设计实现了28位加减计数器。
Then data gained by simulation through the hardware language VHDL were listed out, which proved the validity of the conversion on hardware system.
并列出了一组由VHDL硬件语言模拟得到的转化结果的数据，来证实能在硬件上转化的正确性；
Aiming at the design problem of traffic light controller, this paper puts forward a hardware realization method of traffic light controller with VHDL.
针对交通信号灯控制器的设计问题，提出了基于VHDL语言的交通信号灯控制器的硬件实现方法。
In this paper, a kind of chip of video complex black signal is described with VHDL.
采用VHDL硬件描述语言设计一种再生视频复合消隐信号的专用芯片。
Summarized the concurrent statements and sequential statements of VHDL language, and described their types and the characteristic.
简单概述了VHDL语言的并行语句和顺序语句，描述了其种类和特点。
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