If the circuit under verification is carved out from the design, the input waveforms to the circuit must be configured to be identical to them when the circuit is embedded in the design.
如果被验证的电路是从设计中勾画出的，那么电路的输入波形必须被配置为与当电路被嵌入到设计中时的一样。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
The paper has an emphatical discussion on the study and analysis of the circuit structure and layout structure of these two modules, and makes a lot of SPICE simulation and verification.
课题着重对这两个模块的电路结构以及版图结构进行了深入的研究和分析，并采用SPICE工具进行了模拟验证。
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
In integrated circuit (IC) chips design, the verification is one of the most complex and time-consuming step in the chips design flow.
在集成电路(IC)芯片设计中，验证是芯片设计流程中最复杂、最耗时的环节之一。
The verification of microprocessor design must ensure the correctness of arithmetic circuit.
微处理器电路设计的验证工作必须确保运算电路模块设计的正确性。
It's currently not possible, for example, to automate verification on multiple analog circuits because each circuit is different.
例如，目前不可能实现对多个模拟电路的自动验证，因为每个电路都是不同的。
The circuit functions are verified with altera FPGA chips and the results of the verification and its ASIC synthesis with Synopsys DC are given.
同时还给出了采用现场可编程门阵列(FPGA)芯片对设计电路进行功能验证的结果和ASIC流片的基本数据。
Design circuit for SoC (System on Chip) design verification in FPGA prototype phase and product phase.
设计电路用于片上系统的设计验证，包括FPGA原型阶段和产品阶段。
The present invention provides a method for defect enhancing, the method including: displaying a first image of a part related to the suspicious defect in the circuit during the verification process;
本发明提供了一种用于缺陷增强的方法，该方法包括：在验证过程期间，显示电路中与可疑缺陷相关的部分的第一图像；
Experiment shows that verification, the E1 subslot manner can be used to send and receive data in the circuit.
经实验验证，该电路可以使用E1分时隙方式收发数据。
Because of this, the book is intended for CAD developers and researchers in the verification domain, where formal techniques become a core technology to successful circuit and system design.
因为这，书为计算机辅助设计开发者和在证实领土的研究人员准备，在那里正式的技术对成功的电路和系统设计成为一项核心技术。
Model checking based formal verification is a technique of this kind, and has been successful used in practice to verify complex sequential circuit designs and communication protocols.
基于模型检测的形式化方法就是这样一种技术，并已成功地在实践中应用于对复杂的时序线路设计和通信协议的正确性验证。
Has realized the design requirements through the experimental verification electric circuit completely the basic quota, and the DC-DC conversion efficiency achieves 85%.
通过实验验证电路实现了设计要求的全部基本指标，并且DC - DC变换效率达到85%。
So the efficient verification of the design and implement of circuit must be introduced for building the higher responsible VLSI system.
为了设计和建立高可靠性的VLSI系统，必须对VLSI的设计和实现进行有效的验证。
So the efficient verification of the design and implement of circuit must be introduced for building the higher responsible VLSI system.
为了设计和建立高可靠性的VLSI系统，必须对VLSI的设计和实现进行有效的验证。
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