Balance-tlb (transmit load balancing).
balance - tlb(传输负载平衡)。
However, because of on-chip space limitations, the TLB size can not be increased proportionally.
然而，由于芯片空间的限制，TLB的大小不能成比例地增加。
This difference in performance gain is predictable because the pressure on the TLB cache increases as the size of the database and the memory assigned to the DB2 buffer pools increases.
这两组测试得到的性能结果的不同是可以预测的，因为随着数据库和分配给db2缓冲池的内存的增加，TLB缓存上的压力也随之增加。
Large pages can accommodate more memory in fewer actual pages, so as more large pages are used, more memory can be referenced through the TLB than with smaller page sizes.
大内存页可以用更少的实际页来提供更多的内存，相当于较小的页大小，使用的大内存页越多，就有越多的内存可以通过TLB引用。
The profiling table provides the percentage and number of samples collected for specified processor events such as the number of cache line misses, Transition Lookaside Buffer (TLB) misses, and so on.
评测表提供为特定的处理器事件收集的采样的百分数或数量，比如高速缓存线路故障的数量、传输后备缓存(TLB)故障的数量，等等。
A TLB miss requires accessing a page table that is stored in the main memory, which consumes considerably more processor cycles.
如果TLB没有命中，那么就需要访问存储在主存中的页表，而这样做需要消耗相当多的处理器周期。
An increase in TLB hit rate improves the CPI metric and, therefore, performance of that program.
提高tlb命中率可以提高CP i度量，从而也提高程序的性能。
This is because TLB is able to map a larger virtual memory range.
这是因为TLB能够映射更大的虚拟内存范围。
Chart 2 correlates the performance improvements seen in Chart 1 with the decreased CPI and the corresponding decrease in TLB miss rates.
图2将图1看到的性能提升与减少的CPI和相应减少的tlb失误率关联起来。
One option is to increase the TLB size.
一种选择是增加TLB大小。
TLB is used to try and retrieve translation work that has already occurred, and this is the first place the operating system will look for a process's translated memory segment.
TLB用于尝试和检索已经发生的转换工作，而这是操作系统第一次查找进程的已转换内存段的地方。
The fewer pages would mean that the TLB process would have a higher hit ratio and therefore improved performance.
页数越少，意味着TLB进程将具有更高的命中率，因而性能更好。
TLB is the cache holding the mapping information from the virtual address to the physical page in memory.
TLB缓存包含从虚拟地址到内存中物理页面的映射信息。
TLB cache entry reuse (cache hit) equates to quicker address translation and subsequently faster access to physical memory.
tlb缓存条目重用(缓存命中)意味着更快的地址转换，还意味着对物理内存的更快的访问。
To help address translation, operating systems cache the translated memory addresses by a process called Translation Look-aside Buffering (TLB).
为了帮助地址转换，操作系统通过一个叫做转换后援缓冲（Translation Look-aside Buffering，TLB） 的进程来缓存已转换的内存地址。
And I know I’m stretching you to suggest you to think ten years ahead, but as we noted yesterday, “The wise man looks ahead.” (Proverbs 14:8a TLB)
我知道我在拉你往前走，劝你想想未来十年的生活，正如我们昨天看到的，“通达人的智慧，在乎明白己道。”
To speed up address translation, there is a processor-on-a-chip (PoC) cache and associated logic called translation lookaside buffer (TLB).
为了加快地址转换，架构中有一个 processor-on-a-chip (PoC)缓存和相关的转换后备缓冲器 (TLB)逻辑。
The performance improvement is due to the reduction of Translation Lookaside Buffer (TLB) misses, which occurs because the TLB can now map to a much larger virtual memory range.
性能之所以得到了改进，是因为提高了TranslationLookasideBuffer (TLB)的命中率，这是因为TLB可以映射到更大的虚拟内存范围。
With 16-megabyte and 16-gigabyte pages, a further improvement in TLB hit rate led to proportional CPI gains and, therefore, higher overall throughput.
当使用 16 MB和16 GB页面时，TLB 命中率进一步提高，导致CPI成比例增长，从而取得了更高的总体吞吐率。
Ship the 6.0 type library from Windows 7 RTM via the new type library file msado60.tlb.
通过新的类型库文件msado60 . tlb为Windows7RTM发布6.0类型库。
The performance improvements are due to the reduced translation look aside buffer (TLB) misses.
性能的提高归功于转换表缓存区(translationlook a side buffer,TLB)失败的减少。
The TLB miss rate decreased by 13% compared to the same measurement for 4-kilobyte pages, thereby improving the overall performance of the workload by 13%.
与使用4KB的页面相比，tlb失误率减少了13%，导致工作负载的整体性能提高13%。
"In response to all he has done for us, let us outdo each other in being helpful and kind to each other and in doing good" (Hebrews 10:24 TLB).
为了响应他为我们做的一切，让我们彼此相顾，激发爱心、勉励行善。
Yes they do. Most processors using virtual memory use TLB.
是他们做的。大多数处理器使用虚拟内存使用TLB。
Whenever an instruction is fetched from memory, the instruction pointer is translated via the instruction TLB into a physical address.
无论何时从内存中取一个指令，指令指针都会经指令tlb的翻译后指向物理地址。
In order to optimize performance, including speed and the usage of its memory, CPU usually hires a Translation Lookaside Buffer(TLB) to translate the virtual address into physical address.
为了提高CPU的速度和更有效的管理物理内存，一般都采用转换查找缓冲器（TLB）将虚拟地址转换为物理地址。
The TLB miss overhead represents one important component of the overall CPI metric.
TLB失误的开销是整个CPI度量中的一个重要部分。
Locking TLB entries can ensure that a memory access to a given region never incurs the penalty of a page table walk.
锁定TLB输入能确保对于给出区域的内存读取绝不会导致页表移动的掉失。
By providing TLB (Type libraries) we can pull every function signature and can show every signature to Grid control or on Tree control.
通过提供TLB(类型库)，我们可以拉每个函数签名，并可以显示每个签名到网格控制或树控件。
If you can modify the Interface Definition Language (IDL) source, you can apply type library file (TLB) attributes and import the type library.
如果可以修改接口定义语言(idl)源，就可以应用类型库文件(TLB)特性并导入类型库。
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