In the thesis, we implemented a cell-based timing analysis of a full-custom design, which shows the idea of hierarchical analysis.
本论文实现了全定制电路设计的单元级时序分析，充分体现了层次化的分析思想。
Static timing analysis is widely applied in timing verification because of its high speed and great capacity. The gate delay computing is a critical part of static timing analysis.
静态时序分析由于速度快和容量大而广泛应用于时序验证，而门延时的计算则是静态时序分析中的关键部分。
Implementation of static timing analysis.
静态时序分析的实现。
The timing analysis in the design of digital integrated circuits is described.
文章对数字集成电路设计中的时序分析作了一个概要的介绍。
Static timing analysis is an exhaustive method of analyzing, debugging and validating design performance.
静态时序分析是一种彻底的分析、调试、验证设计的方法。
Responsible for timing analysis, debug and verify on board, communication with circuit engineers for debugging;
负责时序分析、上板调试验证、同电路工程师进行系统联调；
Designers have to spend most of time and energy on timing analysis, because a slight mismatch would lead whole failure of entire logic function.
设计人员通常在时序分析上花大量的时间和精力，因为一个微小的时序问题能导致整个设计的逻辑功能的错误。
We accomplished the full-chip static timing analysis of X microprocessor, and made a detailed analysis such as critical-path checking in the circuit.
参与并完成了X微处理器全芯片的静态时序分析工作，对电路的关键路径等重要信息进行了详细分析。
Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed.
首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。
In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.
文章在静态时序分析的基础上，提出了一种利用关键路径时延信息提高FPGA分割效率的方法。
The timing analysis and si simulation results show that the UHDA system can satisfy the system timing requirements with the help of the si analysis technique discussed in this thesis.
分析和仿真结果表明，通过在设计中运用信号完整性分析方法，本文设计的超高速数据采集系统能满足工作时序的要求。
Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.
最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。
Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.
最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。
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