When both the input conditioning and main-gate flip-flop are logically true, the main gate opens for a period of time that is determined by the timer base divider.
当输入转换和主控门触发器同时为逻辑真时，主控门打开一定时间，这个时间由时基分配器决定。
It includes the time-base circuit, time set and delay circuit, input interface, clear and reset circuit etc.
内容包括时基电路、预置延时电路、输入接口、总清及加电复位等。
It includes the time-base circuit, time set and delay circuit, input interface, clear and reset circuit etc.
内容包括时基电路、预置延时电路、输入接口、总清及加电复位等。
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