But, the Combinational Logic Circuits possible isn't a most simple Combinational Logic Circuits.
但是利用最简逻辑函数实现的逻辑电路却不一定是最简的逻辑电路。
Through examples it proves that the optimal method of the combinational logic based on the rough set is both feasible and effective.
文章提出了基于粗糙集的多输出逻辑函数优化方法，并给出了相应算法；实例验证表明，基于粗糙集的组合逻辑优化方法是可行和有效的。
Through examples it proves that the optimal method of the combinational logic based on the rough set is both feasible and effective.
实例验证表明，基于粗糙集的组合逻辑优化方法是可行和有效的。
Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description.
逻辑综合的功能是对组合逻辑函数的描述进行转换和优化，生成与逻辑功能描述等价的优化的逻辑级纯结构描述。
Gray coding and encoding two One-hot state machine 2 trigger part and the combinational logic part of the combination of two states with separate machines.
Gray编码和One -hot编码两种状态机；2。触发器部分和组合逻辑部分结合与分开两种状态机。
According to a requirement of design, the optimum parameters of combinational logic circuits can be obtained after running the program.
根据设计要求，通过本程序的运行，可获得最佳的组合逻辑电路的参数。
This paper briefly introduces the basic method of transforming data selector into combinational logic circuit of other functions.
简述了用数据选择器转换为其它功能组合逻辑电路的基本方法。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance.
仿真实验结果证明了改进演化算法对于实现函数级数字组合逻辑电路的硬件演化是可行的，并且提高了演化算法的演化效率和收敛性能。
On the basis of the multiple-valued switch-level algebra, this paper proposes a logic design automation algorithm for NMOS and CMOS combinational circuits.
本文在多值开关级代数理论的基础上，提出了适合于NMOS及CMOS组合电路的逻辑设计自动化算法。
The properties of Boolean difference are made use of to derive a new method for fault testing in combinational logic circuits. This method is simpler and different from the traditional one.
本文利用布尔差分的性质，给出了一种不同于传统的求组合逻辑线路故障测试码的新方法，对故障测试有一定的简化作用。
This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.
本实验指导书分为两大部分：组合逻辑，时序逻辑。
In these alternative embodiments, the number of registers exceeds the number of combinational output signals in the one logic module.
在这些替代实施例中，在所述一个逻辑模块中寄存器的数量超过组合输出信号的数量。
To stress the application of Karaugh map on designing of coding circuits in parallel-comparator ADC in terms of the design of combinational logic circuits.
根据组合逻辑电路的设计方法，突出用卡诺图化简逻辑表达式在并联比较型A/D转换器编码电路设计中的应用。
In this paper the writer tries to integrate the design of asynchronos counters of arbitrary carry system with the design of combinational logic circuits in concept and method.
本文试图把时序逻辑电路和组合逻辑电路的设计，在概念上和方法上统一起来。
And combinational logic circuits by using VHDL language and in two ways, comparing the merits of the two implementations and different design processes and ideas.
并且通过应用组合逻辑电路和VHDL语言实现两种方法，对照了两种实现方法的优劣及不同的设计流程和思想。
To model combinational logic, a procedure block must be sensitive to any change on the input.
为了建模组合逻辑，一个过程块必须能够感应到输入的任何变化。
To model combinational logic, a procedure block must be sensitive to any change on the input.
为了建模组合逻辑，一个过程块必须能够感应到输入的任何变化。
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