A deterministic algorithm is proposed for System-on-Chip (SOC) test scheduling.
提出了一种确定性的片上系统(SOC)测试调度算法。
This paper presents the TAM optimization and test scheduling algorithm for multi-clock SOC, and it aims at decreasing test time of multi-clock SOC.
该文提出了用于多时钟域soc的TAM优化与测试调度算法，以减少多时钟域soc的测试时间。
A kind of chip-level test controller which can flexibly carry out the result of test scheduling is presented, which also takes chip test scheduling into account.
本文首次将测试调度问题与芯片级测试控制器设计问题结合起来，提出了一种能够灵活实现各种测试调度结果的芯片级测试控制器设计。
Test scheduling machine failover
测试调度机器失效切换
Test scheduling determines an assignment of cores to test access mechanism such that the overall test application time of system on chip (SOC) is minimized.
测试调度是系统芯片测试的一个重要方面，它用于确定把芯片上芯核的测试集分配给测试存取机制的方法，以使得总的测试时间最少。
Test scheduling determines an assignment of cores to test access mechanism such that the overall test application time of system on chip (SOC) is minimized.
测试调度是系统芯片测试的一个重要方面，它用于确定把芯片上芯核的测试集分配给测试存取机制的方法，以使得总的测试时间最少。
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