Congratulations! You have successfully created a local broker ready to test patterns.
祝贺您！您已经成功创建了一个可用于测试模式的本地代理。
The test suite is made up of test cases, based on one of two available test patterns: operation-level testing or scenario based testing.
测试套件由测试用例构成，并基于以下两种可用的测试模式之一：操作级别的测试或基于场景的测试。
But it's been our experience that with the right tools, project environment, and understanding of the test patterns associated with it, component testing can be both successful and cost effective.
但是，从我们的经验来看，使用正确的工具、项目环境，并理解与之相关的测试模式，组件测试就可以变得很成功有效。
Because this method doesn't use memory to store the test patterns, it can save certain area of the chip.
该方法由于没有采用存储器存储测试模板，所以可以节省一定的芯片面积。
The test patterns TE142 is supplied on sheets of paper or cardboard and backed with self-adhesive foils if requested.
TE142测试卡提供纸张或纸板模式，如果需要也支持自粘箔。
The proposed method can generate simplified test patterns with high fault coverage, and can detect multiple faults as many as possible.
新方法可生成精简的、故障覆盖率高的测试图形，并尽可能多地检测多重故障。
The BIST controller can not only perform traditional memory test algorithms but also generates test patterns required for the logic part.
BIST控制器不仅可以执行传统的存储器测试算法，而且可以生成用于逻辑模块的测试向量。
This paper presents an algorithm of test patterns generation for digital circuits which is called the principal path sensitization method.
本文提出了产生数字电路测试码的一种算法——主路径敏化法。
In our own testing we have discovered a number of common test patterns. In order to encourage a consistent approach for testing they are published below.
在我们的测试中，我们发现有几个共同的测试模式。为了鼓励测试方式的一致性，我们发布了以下规则。
A self-test scheme, under which all test patterns for adder under test in VLSI are produced by the adder self, is presented based on arithmetic additive generator.
基于算术加法测试生成，提出了VLSI中加法器的一种自测试方案：加法器产生自身所需的所有测试矢量。
The whole experiment demonstrates that monitoring the quality of CCD process and analysing failure of the device by microelectronic test patterns is practical and reliable.
整个实验表明，用微电子测试图形监控CCD工艺、分析器件失效，是可行可靠的。
For all benchmark circuits, the method is able to encode all deterministic test patterns using an LFSR whose size is equal to the maximum number of care bits in a test pattern.
对于所有的实验电路，通过使用级数为确定性测试向量的确定位数量最大值的线性反馈移位寄存器，本策略可以编码所有的确定性测试向量。
It is shown that any feedback bridging faults between primary inputs and the primary output in any general combinational networks can be betected by using only two test patterns.
证明了在任何组合电路中，只需两个测试码便能测试出所有可能的初级输入与输出端之间的短路故障。
This paper not only gives the test results of frequency-domain but also gives the test patterns of time-domain, and introduces the advantage and principle of the two test methods.
论文不仅给出了频域测试结果图还给出了时域测试图，并对两种测试方式的优势和原理进行了介绍。
In order to reduce the storage requirements for the test patterns, a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed.
为了减少测试向量的存储需求，提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。
In order to reduce the storage requirements for the test patterns, a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed.
为了减少测试向量的存储需求，提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。
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