Test case generation for acceptance tests differs from other test phases due to some distinct deviations between the underlying premise of this test level and the others.
验收测试的测试用例的生成在不同的测试阶段是不同的，这是由于这个和其它测试水平潜在的前提之间存在一些明显偏差所导致的。
Facilitate governance practices regarding privacy standards for test data generation by capturing privacy policies and business objects for downstream tasks.
通过为下游任务捕捉隐私策略和业务对象，帮助治理生成测试数据的隐私标准。
It helps you perform all steps in the project lifecycle including build, deployment, test, report generation, and documentation.
它可以帮助您执行项目生命周期中的所有步骤，包括构建、部署、测试、报告生成和记录。
As you saw with configuration, supporting configurable test involves managing test suite generation.
从配置中可以看到，支持可配置的测试需要管理测试套件的生成。
Generation of test messages, based on the service description (WSDL).
根据服务描述(WSDL)生成测试消息。
Figure 2: First method in the grade test data generation program.
图2：成绩测试数据生成程序中的第一个方法。
As a simple example of this, I have tried to generate tests for the bowling game program using two of the better known test generation tools. The interface to the bowling game looks like this.
作为一个简单的示例，我试着使用两款知名的测试生成工具来为保龄球游戏程序生成测试代码。
After the test generation process is complete, the test suite will open in the test Editor view.
当测试生成过程完成之后，测试集将在TestEditor视图中打开。
In addition, its built-in data correlation filters detect variable data, as well as preparing tests for data-driven load test generation.
另外，它的嵌入式数据相关性过滤器能够检查可变数据，并根据数据驱动加载测试需求进行测试。
Those traditional test generation algorithms are not applicable any more.
那些传统的测试生成算法已不再适用。
A new test-code generation model, intended to better support the customisation of generated code.
一个新的测试代码生成模型，以便更好地提供对生成代码进行定制的支持。
Recently defence firm Lockheed Martin has received a $1.1 million contract from the US Army to test its next-generation HULC exoskeleton.
目前，军火商洛克希德马丁公司为了测试下一代HULC外置骨骼，已经同美国陆军签订了110万美元的合同。
Two main aspects in VLSI testing, fault simulation and test generation, are researched in this dissertation.
本文对VLSI测试中的两个主要问题—故障模拟和测试产生进行了深入的分析和研究。
Rational Performance Tester simplifies the test-creation, load-generation and data-collection processes to help ensure the ability of applications to accommodate required user loads.
RationalPerformance Tester简化了测试的创建、负载的生成，以及数据的收集过程，帮助确保了应用程序适应所需的用户负载的能力。
In addition, the detailed analysis of some frequently used memory test algorithms and brief analysis of some test generation algorithms for VLSI are also included in this paper.
另外本文还比较详细的分析比较了常用的存储器测试算法，简要分析了VLSI测试生成算法。
This paper describes state transition fault and collapsing of test generation basis of the character of fixed fault.
详细分析了固定故障所反映出的状态变换特征，提出状态变换故障模型以及相对应的测试生成压缩方法；
Using Binary Decision Diagrams, this paper proposes a test generation method for functional level digital circuits.
本文利用二叉判定图提出了对功能级数字电路的一种测试产生方法。
The result indicates that the technology manipulates easily and is effective, the fault coverage reaches 90%, it is a feasible test generation technology.
仿真结果表明，该方法操作简单、有效，故障覆盖率达到了90%，是一种很可行的存储器板测试生成方法。
The implementation of automatic test generation and fault diagnosis is also discussed.
还讨论了测试码自动生成和故障诊断的具体实现方法。
A kind of model data and the preprocessing method for the logic circuit test generation system (TGS) are presented.
讨论了逻辑电路测试生成系统(简称TGS)中使用的一种模型数据及预处理方法。
Low coverage indicates a process problem, which might require test generation technique to be improved, or training to be imparted to the tester.
低的覆盖率表明方法有问题，可能是测试生成技术需要改进，也可能需要给测试人员提供培训。
This paper presents an interoperability test generation method based on the formal model, Communicating Multiport Finite State Machines.
文章提出了一种基于通信多端口有限状态机模型的协议互操作性测试生成方法。
Facing the challenge of design scale of VLSI becoming larger, except for circuit parallel, the existing basic parallel approaches cannot solve test generation complexity problems radically.
面对VLSI设计规模日益增大的挑战，除了电路并行以外，其它已有的基本并行策略都无法从根本上解决测试生成的复杂性问题。
The test generation efficiency is higher comparing with other algorithms.
与其他算法相比，测试生成效率明显提高。
However, the existing circuit parallel test generation algorithms fail get good results, especially for sequential circuit.
然而，已有的电路并行测试生成算法并未取得理想的结果，尤其对时序电路。
This paper presents a high speed test generation method specifically for upper large scale combination circuit (ULSCC) and full scan designed circuit.
针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法。
Besides fault collapsing, this paper also proposes some techniques, such as code collapsing, change of the ending rules to optimizing the test generation algorithm.
结合故障精简，本文通过编码压缩、变化终止规则等方法进一步优化了全速电流测试方法的测试产生算法。
This paper propose a functional fault for delay faults in combinational circuits and describe a functional test generation procedure based on this model.
提出一种用于测试组合电路中延迟故障的新功能故障模型，讨论该模型的功能测试生成。
A constraint extraction method and a constraint path delay test generation algorithm are developed.
研究并实现了约束提取及约束下的非强健通路时延测试产生算法。
A constraint extraction method and a constraint path delay test generation algorithm are developed.
研究并实现了约束提取及约束下的非强健通路时延测试产生算法。
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