Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive-applied technique.
固定频率源可以在在通讯系统和雷达系统中作为本机振荡器，也可以作为数字电路的基准时钟信号，因此得到了广泛的应用。
And it presents a efficacious method to enhance precision of real time control, which changes value of clock interrupt frequency by changing divided frequency of system tinier.
同时给出了一种提高实时控制精度的有效方法，即通过改写系统定时器的分频值达到改变定时器时钟中断频率的值。
Therefore, the clock frequency directly affect the speed of MCU, clocking circuit and the quality of directly influence the stability of single-chip microcomputer system.
因此，时钟频率直接影响单片机的速度，时钟电路的质量也直接影响单片机系统的稳定性。
This paper introduces the method of clock calibration to VCXO in system, based on GPS and CPLD. It can solve the problem of frequency offset because of Crystal worse behavior in Long-term use.
本文还给出了基于GPS芯片和CPLD，对系统压控晶振时钟进行校准的实现方法，有效解决了由于长时间使用，晶振自身特性变化，造成的频率偏移现象。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
The system based on the frequency synthesizer can offer a high accuracy, high stability and low jitter clock for a high speed and high precision backplane test platform.
该时钟板基于频率合成器来产生高精度、高稳定度、低抖动的时钟，用于高速高精度背板测试平台。
Absrtact: Along with the increase of digital system working frequency, clock period gets shorter, timing of the system becomes more complex.
摘要：随着数字系统的工作频率的不断提高，时钟周期逐渐变小，而系统时序却越来越复杂。
The clock signal is obtained by using a frequency doubler which USES a modified XOR topology, so that the complexity of the system is reduced.
改进异或门拓扑结构实现的二倍频器，结构简单、实用，降低了电路复杂度。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
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