Enables or disables the SATA drives connected to the system board.
启用或禁用SATA设备连接到主板上。
The main goal is to design a DSPminimum system board for this paper.
DSP最小系统板硬件设计是本次论文的主要任务。
Buses also link the CPU to various other components on the system board.
巴士也连接的CPU系统板上的各种其他组件。
Minimum system board with the electrical schematic diagram of the simulation system has.
最小系统板与电模拟系统的原理图都有。
Experimental introduction of the SP3 system board structure and layout, and user guides.
介绍了SP3实验板的系统结构和布局，用户指南。
If you feel comfortable with it, try checking the power Configuration options in your system board setup.
如果你觉得不舒服，请检查您的系统板安装电源配置选项。
The hardware components of the system are divided into two parts: minimum system board and expansion board.
整个系统的硬件组成分为两个部分——最小系统板与扩展板。
The motherboard is sometimes alternatively known as the mainboard, system board, or, on Apple computers, the logic board.
主板有时或者称为主板，系统板，或苹果电脑上的逻辑电路板。
It indicates that a technician replaced the system board or component but failed to input the new serial number in the system.
这条信息表示主板或计算机其它硬件做技术性替换后，向系统输入新序列号信息时失败。
The part of hardware on the system is made up of the minimum system board, measure to turn board and speed modification board.
系统的硬件部分由单片机最小系统(主控板)、测速部分及调速部分三大块组成。
This paper mainly analyzes the application of the IBIS model in the system board design and system clock design for mobile computers.
本文主要分析了IBIS模型在移动微机板参设计和在系统时钟设计中的应用。
Peripherals are real devices, such as graphics CARDS or disks controlled by controller chips on the system board or on CARDS plug ged into it.
外设是一些物理设备，比如说图象卡或者磁盘，它们受控于位于主板或者主板上插槽中的控制芯片。
They are the one's that can be programmed and reconfigured the logic functions while on the system board which is suitable for faster prototyping.
它支持在系统编程，在系统重构器件的逻辑功能，很适合产品的样机开发。
The paper USES DSP system board designed by ourselves. Its main task is data process real-time control and expert Fuzzy neural network control scheme.
采用了自行设计的DSP系统板，它主要完成数据处理及实时控制以及专家模糊神经网络的控制方案。
In this case though, only the first system board Ethernet adapter of any node was utilized and by one instance of netperf along with one instance of netserver.
但是，在这种测试中，只使用任何节点的第一个系统板载以太网适配器，而且只使用一个netserver实例和一个netperf实例。
Figure 12 shows the network stream throughput and CPU utilization for the test runs while using the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图12显示测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
The first of the netserver scalability tests utilized a single instance of netserver on each of the two system board Ethernet adapters on the first node of the SUT.
第一个netserver可伸缩性测试在SUT的第一个节点的两个系统板载以太网适配器上各使用一个netserver实例。
The IBIS model is used to help get exact information in the integrity constraint design of system board level or multiple board level signals for analysis and calculation.
IBIS模型可以帮助设计者在系统板级或多板信号完整性约束的设计中获取准确的信息，以进行分析和计算。
Figure 5 shows the network stream throughput and CPU utilization for the netperf scalability test runs while using the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图5显示netperf可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
Figure 1 shows the network stream throughput and CPU utilization for the netserver scalability test runs while using the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图1显示netserver可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
Figure 7 shows the network stream throughput and CPU utilization for the netserver scalability test runs while using the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图7显示netserver可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
Figure 8 shows the network stream throughput and CPU utilization for the netperf scalability test runs while utilizing the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图8显示netperf可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
Figure 2 shows the network stream throughput and CPU utilization for the netperf scalability test runs while utilizing the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图2显示netperf可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
Figure 11 shows the network stream throughput and CPU utilization for the netperf scalability test runs while utilizing the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图11显示netperf可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
Figure 3 shows the network stream throughput and CPU utilization for the bidirectional scalability test runs while using the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图3显示双向可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
Figure 6 shows the network stream throughput and CPU utilization for the bidirectional scalability test runs while using the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图6显示双向可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
Figure 4 shows the network stream throughput and CPU utilization for the netserver scalability test runs while utilizing the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图4显示netserver可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
Figure 10 shows the network stream throughput and CPU utilization for the netserver scalability test runs while utilizing the system board Ethernet adapters on 1, 2, and 4 nodes of the SUT.
图10显示netserver可伸缩性测试的网络流吞吐量和系统cpu利用率，分别使用SUT中1、2和4个节点上的系统板载以太网适配器。
The second netserver scalability test used all four system board Ethernet adapters on the first two nodes and the third test used all eight system board Ethernet adapters on all four nodes.
第二个netserver可伸缩性测试使用前2个节点上的所有4个系统板载以太网适配器，第三个测试使用所有4个节点上的所有8个系统板载以太网适配器。
Come on, folks: get on board with ditching the outdated tip system.
来吧，伙计们：我们一起抛弃过时的小费制度吧。
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