The ERCCL logic is not implemented through a switch logic network but through capacitance coupling, which reduces its turn-on resistance and adiabatic losses.
利用电容耦合，而不是开关逻辑网络进行逻辑求值，相对减小了导通电阻和绝热损失。
The CEC technique compensates the sampling bandwidth by eliminating the impact from finite on-resistance of the sampling switch, and avoids increasing clock feedthrough and charge injection.
该技术通过消除采样开关有限导通电阻的影响，补偿了采样带宽，并避免了时钟馈通和电荷注入的加剧。
It is specifically designed to operate at voltages down to 0v across the switch elements while maintaining good speed and on-resistance characteristics.
它是特别设计，在电压下降到0V时整个开关元件，同时保持良好的速度和导通电阻特性。
By compensating with P-type bootstrapped switch, this circuit can overcome nonlinear distortion, which is generally introduced by signal-dependent on-resistance, and improve sampling resolution.
采用P型栅压自举开关补偿技术，可以有效地克服采样管导通电阻变化引入的非线性失真，提高采样精度。
By compensating with P-type bootstrapped switch, this circuit can overcome nonlinear distortion, which is generally introduced by signal-dependent on-resistance, and improve sampling resolution.
采用P型栅压自举开关补偿技术，可以有效地克服采样管导通电阻变化引入的非线性失真，提高采样精度。
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