SCFL circuits are used because of the higher speed compared to static CMOS.
电路采用源极耦合场效应管逻辑（SCFL），与静态CMOS逻辑相比具有更高的速度。
QSERL 4 bit carry ripple adder (RCA) is designed and compared with static CMOS counterpart.
设计了4位QSERL串行进位加法器(RCA)电路，和相应的CMOS电路进行了功耗比较。
Bandwidth and offset of CMOS folding preprocessing circuit are the main factors, which limit the dynamic and static characteristics of folding-interpolating ADC.
CMOS折叠预处理电路的带宽和失调是限制折叠内插式adc的动态和静态特性的主要原因之一。
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
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