Square-root raised cosine roll-off digital filter was widely applied to baseband shaping filter and match filter in modern digital communication.
现代数字通信中广泛采用平方根升余弦滚降数字滤波器作为基带成形滤波器和匹配滤波器。
This paper introduces design, optimization and implementation with FPGA of square-root raised cosine roll-off digital filter.
介绍了平方根升余弦滚降数字滤波器的设计和优化方法，并提出了用FPGA实现其硬件电路的方案。
This paper introduces design, optimization and implementation with FPGA of square-root raised cosine roll-off digital filter.
介绍了平方根升余弦滚降数字滤波器的设计和优化方法，并提出了用FPGA实现其硬件电路的方案。
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