High speed data bus technology is one of the core techniques in avionics.
高速数据总线技术是航空电子中的关键技术之一。
Absrtact: High speed data bus technology is one of the core techniques in avionics.
摘要：高速数据总线技术是航空电子中的关键技术之一。
High speed data bus is the key technology in avionics integration for advanced fighters.
高速数据总线是先进军机航空电子综合化的关键支撑技术。
In this dissertation, the detail methods of implementing high-speed data bus system which is based on OFDM technique are researched.
本文主要对以OF DM技术为核心的高速数据通信总线的若干关键技术和具体实现进行了研究。
High speed data bus technology is one of the key technologies in avionics integration, which has direct influence on the performance of the avionics system of tactical aircraft.
高速数据总线技术是航空电子综合化最重要的支撑技术之一，直接决定整机航电系统综合化程度的高低。
To the bottleneck problems of bus bandwidth and transmission speed in traditional data acquiring systems, this paper presents and implements a 200m data acquiring system based on PCI bus.
本文针对传统的数据采集系统中存在的总线带宽、传输速度等瓶颈问题，提出了并实现了一个基于PCI总线的200m数据采集系统。
The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal.
视频介绍上的并行lvcmos总线串行数据序列化为一个高速差分信号。
The peripheral bus that conform the PVCI standard usually used to connect IPs with low speed and low data width.
而符合PVCI标准的外设总线上连接的往往是低速度、低数据宽度的IP。
As a new computer bus interface criterion, USB ap-plies to the high-speed data collecting system.
通用串行总线作为一种崭新的微机总线接口规范，其特点使其非常适合高速数据采集系统。
In fact, in order to realize image data real-time collecting and rapid storage, uniting PCI bus and SCSI bus which make system hold high speed data throughput provides sufficiency observation data.
在实际的工作中，把PC I局部总线和SCSI系统总线结合起来，使整个系统拥有高速的数据吞吐量，以期实现图象数据的实时采集和快速存储，为实时处理和事后分析工作提供充分的观测数据。
The CLB bus is a kind of on-chip system bus which is usually used to connect IPs with high speed and high data width.
CLB总线是一种片上系统总线，一般用来连接高速度、高数据宽度的IP。
Using field bus, it can increase data transmission speed and reliability.
采用现场总线传输信号，提高了数据传输速度及可靠性。
Lastly, the clock speed of the bus feeding scan chain data to the pins of the DUT is increased by multiplexing the scan chain data being transferred to the bus.
最后，通过多路传送被传输到总线的扫描链数据，可以提高输送扫描链数据到DUT管脚的总线的时钟速度。
The dual-ported RAM is a kind of special memory, and the bus data share between double high-speed microprocessors is carried out by using it.
双端口ram是一种特殊的数据存储芯片，利用双端口ram可以实现双高速单片机总线方式的数据共享。
This ECS employs modular design, and achieves real-time communication of data with CAN bus, and thus is able to control the speed of engine and monitor the system.
该ECS采用模块化设计思想，利用CAN总线进行数据信息的实时通讯，以实现电子调速和系统监控等功能。
PC and DSP exchange data using high speed static RAM and bus arbitration circuit and corresponding handshake signal is designed to ensure the correct reading and writing RAM.
PC与DSP的数据交换采用高速静态RAM，并设计总线仲裁电路及相应的握手信号，以保证PC与DSP双方对RAM的正确读写。
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.
该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制，通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
It is proved by practical application that DSP control circuit based on PCI bus can not only increase the speed of data communication, but also the reliability of the system.
实践表明基于PCI总线的DSP控制电路不仅提高了数据通讯的速度，而且提高了系统控制板卡的可靠性。
This paper gives a serial transmission method which bases on the I2C BUS and its division. Wehave effectively solved the data delay in high speed serial data transmission system.
本文提出了一种基于I2C总线及其分割技术的串行传输方法，可有效解决高速串行传输系统中的数据延迟问题。
Aim To study the design and realization of ultra high speed data acquisition and DSP system based on VME computer bus expended for instruments (VXI) bus.
目的研究VME计算机总线扩展的仪器标准总线(VXI)超高速数据采集与DSP系统的设计与实现。
The paper states the design method of high speed data acquiring system based on PCI bus.
研究了基于PCI总线的高速数据采集系统的设计方法；
It introduces how to design a PCB board of high speed data transmitting system based on PCI part bus, including the discussing of hardware agreement and software agreement.
文章介绍了如何通过PCI局部总线实现高速的数据传送，即介绍了对PC I接口板的开发介绍，其中包括它的硬件协议和软件协议的讨论。
In the paper, a design example of the high speed data acquisition system based on PCI bus of computer with CPLD as a control kernel is introduced.
给出了一个以CPLD为控制核心的基于计算机PCI总线高速数据采集系统的设计实例。
This system with the control core of 80c552 single chip processor adopts bus isolation technique, realizing the time-sharing processing of high-speed data collecting and data processing.
该系统以80c552单片机为控制核心，采用总线隔离技术，实现高速数据采集与数据处理分时进行。
Traditional analysis tools only cover the single low speed bus and test signals in physical layer and data layer respectively.
传统方法只能分析系统中的单一低速总线，分别观测物理层信号和数据层数据进行分析。
The research puts forward the methods of solving the problems by analyzing the limitations which MIL-STD-1553 B data bus protocol possesses in high speed data communication.
通过对美国军用标准MIL-STD-1553B总线协议在高速数据通讯中受到限制的分析，提出了现实解决办法。
This thesis presents a system architecture of six channel high speed data acquisition on PCI bus and implement it.
提出并实现了一种基于PCI总线六通道高速采集系统的结构。
This thesis presents a system architecture of six channel high speed data acquisition on PCI bus and implement it.
提出并实现了一种基于PCI总线六通道高速采集系统的结构。
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