VHDL Silicon compiler is a supplementary tool of the IC CAD system-XUECAD.

VHDL硅编译器是XUECAD集成电路自动设计系统的一个辅助工具。

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VHDL silicon compiler is a supplementary tool of the IC CAD system-XUECAD. The algorithms of modified VHDL silicon compilers placing and routing are introduced in this paper.

VHDL硅编译器是XUECAD集成电路自动设计系统的一个辅助工具。本文将着重介绍改进后的VHDL硅编译器的布局、布线算法。

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Code generated for Silicon Labs single-cell C80519XXF by a non-OCG compiler results in an average of 108 cycles to execute the interrupt service routine and main loop overhead for each sample of data.

非ocg编译器针对SiliconLabs单电池供电c 80519 XXF所产生的代码，每次数据采样平均会有108个周期来执行中断服务程序和主循环。

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Code generated for Silicon Labs single-cell C80519XXF by a non-OCG compiler results in an average of 108 cycles to execute the interrupt service routine and main loop overhead for each sample of data.

非ocg编译器针对SiliconLabs单电池供电c 80519 XXF所产生的代码，每次数据采样平均会有108个周期来执行中断服务程序和主循环。

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