The design and realization of SHARC parallel process system based on VME bus were studied.
研究基于VME总线SHARC并行处理系统的设计与实现。
Chapter 3 presents the interior architecture of SHARC processor and the parallel system consisted of multi-processor.
第三章介绍了SHARC处理器的内部结构，以及由多片处理器组成的并行处理系统。
SHARC Processors also integrate many peripherals designed to simplify hardware design, minimize system design risks, and reduce end-customer time to market.
SHARC处理器还集成了许多外设，旨在简化硬件设计，最大限度地减少设计风险，并最终缩短上市时间。
This paper introduces a method to implement the algorithm of digital multi beam forming in high performance DSP SHARC processor, and the parallel processing is discussed.
文中介绍了一种采用高性能DSP处理器SHARC实现实时数字多波束形成的处理方案，着重于其中的并行处理。
Third generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market.
第三代SHARC处理器还集成了专用外设，以简化硬件设计、减小设计风险，并最终缩短上市时间。
Third generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market.
第三代SHARC处理器还集成了专用外设，以简化硬件设计、减小设计风险，并最终缩短上市时间。
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