• The new data process path in Baseband is constructed to optimize hardware resource when it is realized by the means of serial bit processing.

    给出新的蓝牙基带数据处理路径结构,采用串行方式实现优化硬件资源

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  • The most obvious issue is that the interface in Listing 6 requires a JNI call for each bit set or retrieved, as well as a JNI call to read a byte from, or write a byte to, the serial port.

    显著问题就是清单6中的接口设置检索每个以及串行端口读取字节或者串行端口写入字节都需要一个JNI调用

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  • Serial number: A unique 32-bit non-zero positive number.

    序号Serialnumber):一个惟一的32 位非零正数

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  • Using binary notation, 26 movable bit levers inside each bit serial adder convert the swing from the pendulum into a visible notation on the clock.

    使用二进制表示法每个26串行加法器动产杠杆转换成一个钟摆摆动的时钟可见符号

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  • Below the planetary display, each bit serial adder controls one element of the display, the orrery, each of them corresponding to calculate that planet's orbit.

    下面显示行星每个串行加法器控制,显示元素太阳系仪,其中对应计算地球的轨道。

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  • The bit serial adder system was chosen over a normal gear system because of the number of gears it takes to make the clock's calculations.

    串行加法器系统选择一个由于齿轮齿轮系统正常需要使时钟计算

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  • The first part realizes the collection of the serial data by the AD574A and two CD4051 carrying out the 16-Channal 12-Bit A/D transition.

    模块中主要分为部分一部分AD574A芯片两个多路开关CD4051实现16路12位A/D转换,完成串行数据采集

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  • The serial data stream from the DOUT pin has a channel identifier bit and a mode identifier bit, which provide information about the channel converted and the current mode of operation.

    DOUT引脚串行数据通道识别一个模式识别位,提供所转换通道和当前工作模式的相关信息

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  • The implementation scheme of digital latch system with 7 bit serial code is discussed and tested. The obtained results show the structure of system designed by this method is simple and practical.

    本文7串行数字系统一逻辑命题进行实施方案探讨实验证明这种方法设计的系统结构简单实用

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  • After video information read by FPGA, serial video information is transformed into parallel format by Bit-Plane Separation technology first, and then sent to video cable.

    FPGA读取视频信息位面分层技术串行视频信息转换并行数据送到视频电缆上。

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  • We have shown that band-limited interface jitter has a strong relationship to the bit structure of the serial interface code, and hence can be highly correlated with the transmitted audio data.

    我们已经表明频带有限接口抖动很强关系串行接口代码结构因此可以高度相关音频数据传输

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  • The serial structured decoder can decode one bit per cycle. Because the structure of UVLC(Universal Veriable Length Code) is fixed, "first one detector"is designed to decode UVLC.

    变字解码模块核心基于桶形移位器的并行解码结构,使用该结构的解码速度比串行结构更快。

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  • The technique used by most electromechanical serial? devices such as teletypewriters, with this technique, each character consists of three parts: a start bit, the data bits and a stop bit.

    多数机电串行设备电传打字机所经常使用种传输技术。采用这种技术时,每个字符一个起始、干数据一个停止部分组成。

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  • Baud: The rate at which data is received or transmitted in serial: one baud is one bit per second.

    波特连续接收传输数据速率波特定义为每秒一个比特

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  • It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.

    内置功耗高速16位不失码采样adc内部转换时钟一个多功能串行接口

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  • Controller and sensor adopt 8-bit PIC serial single chip processor PIC16F84A and photoelectric interpretation device TLP909 respectively.

    控制器传感器分别采用8位PIC系列单片机pic 16f84 A和光电判读器TLP909。

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  • Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.

    设置控制编程利用3SPI兼容串行接口来完成

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  • This paper presents the design of extended interface in serial communication with 8n-bit binary number.

    本文给出了8n二进制串行通讯扩展接口设计

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  • With the serial communication into more applications, so in some applications, the need for communication of message identification bit allocation proposed standardization requirements.

    随着串行通讯进入更多应用领域,因此,一些应用里,需要通讯功能报文识别提出分配标准化要求

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  • The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.

    新的法器采用比特串行方式,使得硬件结构更加规则减少了原有乘法器关键路径的延迟

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  • The driving component includes: a N-bit serial buffer, a K-bit extension buffer, a N-bit video data buffer and N driving current output ports.

    驱动元件包括N个位缓冲器,一K个位的延伸缓存器,一N个位的影像资料缓存器,N个驱动电流输出端口

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  • We introduced the application of a serial of self-made instruments such as electric knife bit, retractor, deep knotter in minicholecystectomy(MC).

    介绍自制器械包括刀头宽头拉钩深部打结器小切口胆囊切除术应用

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  • A new bit-serial modular multiplication based on optimal normal and shifted canonical was presented.

    研究中提出新的基于正规基和正则基的比特串行乘算法实现方案。

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  • It contains a low power, high speed, 18-bit sampling ADC and a versatile serial interface port.

    内置功耗高速18位采样adc一个多功能串行接口端口

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  • It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.

    内置16位高速采样adc内部转换时钟、一个内部基准电压源(缓冲)、纠错电路以及串行并行系统接口端口

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  • Record bit serial number.

    记下钻头系列号和型号。

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  • Thus, tuning can be accomplished via a 2-byte serial transfer to the 16-bit N register.

    因此通过16比特N寄存器2字节串行转换调谐可以实现

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  • Serial 16-bit DAC8550 successful application of the user manual and debug the program, C can be applied to any written compilation environment.

    串行16位 DAC8550应用用户手册调试成功程序C可以应用任何编译环境。

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  • Serial 16-bit DAC8550 successful application of the user manual and debug the program, C can be applied to any written compilation environment.

    串行16位 DAC8550应用用户手册调试成功程序C可以应用任何编译环境。

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