This paper proposes a novel efficient area reduction solution for hardware implementation of the advanced encryption standard (AES) algorithm which works in SSX11-140 secure processor architecture.
给出了在一种安全处理器(SSX11- 140)中有效缩减AES算法硬件实现面积的设计方案。
As a result, Geronimo will run in a more secure configuration and environment, and processor and memory utilization will be more efficient.
最终Geronimo将运行在更为安全的配置与环境中，同时处理器和内存也将得到更有效的利用。
As a result, Geronimo will run in a more secure configuration and environment, and processor and memory utilization will be more efficient.
最终Geronimo将运行在更为安全的配置与环境中，同时处理器和内存也将得到更有效的利用。
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