Each CUDA-capable GPU node includes local DDR3 SDRAM as well as a 16-lane PCI Express? gen2 interface to the system backplane, providing maximum data throughput direct to GPU memory.
每个CUDAGPU节点包括本地的DDR3SDRAM以及一个16通道PCI二代系统的背板接口，直接向GPU内存提供最大的数据流量。
Each P512 module offers 32 megabytes soldered, FPGA-controlled DDR2 SDRAM and an LVDS channel with a connection speed of 230 MHz and 86 megabytes per second.
每个P 512模块提供32兆比特焊接的、现场可编程门阵列控制的DDR2 SDRAM并具有230mhz和每秒86MB速度的LVDS通道。
The biped runs on an x86 AMD Geocode 500 MHz CPU, 256MB SDRAM, 2GB flash memory, and lithium polymer batteries that last about 90 minutes per charge.
机器人内部装有一颗500MHz频率的AMDGeocode X86处理器，配有256MB内存，2GB闪存，配用的锂电池续航时间长达90分钟。
The IPN250 combines a single GT240 96-core CUDA GPU with an Intel Core2 Duo host processor operating at 2.26GHz and 8 GBytes of DDR3 SDRAM to deliver up to 390 GFLOPS of performance per card slot.
IPN250结合了一个GT240 96核心CUDAGPU，英特尔酷睿2.26GHz双核处理器和8G DDR3SDRAM，可以提供每卡高达390GFLOPS的运算性能。
Structure and work principle of SDRAM chip (MT48LC16M16A2TG-75IT) is analyzed. Internal architecture and workflow of SDRAM controller is confirmed. Furthermore, its control and data path is designed.
分析了SDRAM芯片(MT 48lc16 M 16a2tg- 75it)的结构和工作原理，确定了内存sdram控制器的内部结构和工作流程，完成了内存sdram控制器的控制通路和数据通路设计。
A dynamic SDRAM access scheduler according to modern SDRAM technology and memory access scheduling algorithms is proposed in this paper.
在本文中提到动态sdram根据现代sdram技术进入调度程序和存储器进入调度的算法。
A digital audio recording, storing and playing system based on FPGA includes the processing of audio signals, the access to SDRAM and the display on LCD (character).
基于FPGA的数字音频采集、存储和播放系统实现了数字音频信号的处理、SDRAM存取以及字符型LCD显示等功能。
And then it presents a novel memory controlling architecture with DDR SDRAM according to the characteristics of the modern DRAM storage devices.
然后，结合现代DRAM存储设备的特点，提出了一种以ddr SDRAM为存储设备的新的内存控制器的结构。
The image is buffered using SDRAM and the high-speed high-resolution image-acquisition has been implemented.
设计了采用SDRAM进行图像缓存的方法，实现高速高分辨率图像的采集。
For the problem of huge data storage, use SDRAM to store the data, and use FPGA to control SDRAM to complete the transpose.
为了解决数据量庞大、高速数据存取的问题，本文采用了FPGA芯片和同步动态存储器(SDRAM)来实现矩阵转置运算。
Based on the analysis of the SDRAM and DDR memory architecture, this paper presents the design principals of MBM and offers the implementation and the actual waveforms.
在详细分析了SDRAM和DDR存储器结构的基础上，提出了MBM的设计思想，并给出了其实现方法和实际波形。
The design of CPLD has adopted the output clock of image sensor to write SDRAM.
CPLD电路设计采用图像传感器的输出时钟触发sdram写过程。
Based on SDRAM, we adopt DLL technology and catch information twice on time signal, and it is so-called DDR technology.
以sdram为基础采用DLL技术，并对时钟信号进行两次抓取资料，形成DDR技术。
Video data stream is stored into SDRAM via It's controller.
视频数据流通过该控制器接收，然后存入片外sdram中。
The paper introduces the application of SDRAM and its general controller based on FPGA in the PDP video storage system.
介绍了SDRAM及其基于FPGA的通用控制器在PD P视频存储系统中的应用。
Controller is calculated for the standard the memory DDR2 SDRAM and allows the possibility of programming latency.
控制器的计算标准内存的DDR2SDRAM，并允许的可能性，方案延迟。
This article introduces that in a new design of radar raster-displaying terminal, SDRAM is used as video frame memory and FPGA is adopted to carry out the process of control circuit.
SDRAM作为雷达光栅显示视频帧缓冲存储器，通过FPGA器件实现对SDRAM的控制，已成功应用于一款雷达光栅显示终端。
The embedded system in this thesis include CPU , memory part , LCD part, touching screen, keyboard, FLASH, SDRAM and internet interface and so on.
本论文的嵌入式硬件环境，包括CPU的外围时钟电路，复位电路，存储器单元，LCD模块，触摸屏，键盘，FLASH，SDRAM，网络接口等部分。
SDRAM (Synchronous Dynamic Random Access Memory) is the best choice with the characteristic of high integration, low power, high reliablity, strong function.
同步动态随机存储器SDRAM凭借其集成度高、功耗低、可靠性高、处理能力强等优势成为最佳选择。
Wait until SDRAM self-refresh is effective.
设置延时程序使SDRAM的自我刷新有效。
The interface between SDRM and FPGA was designed, and mutual communication between the serial port of the computer and SDRAM was realized.
在此系统之上实现了计算机串口与SDRAM之间的相互通信。
Parameter table module is the SDRAM memory controller interface for reading parameter information when image processing.
参数表模块主要实现SDRAM存储器的控制器接口，用于图像处理时读取参数信息。
We design a simple SDRAM controller in FPGA to interface with SDRAM, its main tasks are initialization, periodic refreshing, continuous reading and writing.
并在FPGA中实现了一个简化的SDRAM控制器，用以完成对SDRAM的初始化、定时刷新、连续读写等功能。
The Memory chip is DDR SDRAM memory type chip.
内存芯片的DDRSDRAM内存芯片的类型。
This paper based on the mechanism of DDR-SDRAM, gave a way to construct a DDR-SDRAM controller based on WISHBONE bus protocol, and also introduced a forecast method to improve DDR's performance.
SDRAM是当今一种流行的高速存储器。通过和普通sdram存储器对比，阐述了WISHBONE总线协议下ddr存储器控制器的设计方法和注意事项，并提出一种提高DDR工作效率的预测机制。
The SDRAM has become the chief choice of the buffer storage because of its high speed, great capacity, and low price; but due to its complex control timing, it cannot directly interface with DSP.
同步动态随机存储器（SDRAM）具有高速，大容量，价格低廉等优点，因而成为缓冲存储器的首选，但是SDRAM控制时序比较复杂，不能与DSP直接接口，这极大地限制了它的广泛应用。
Because of cost, capacity, transferring rate and power, SDRAM is more suitable than SRAM for high-speed digital image processing system.
综合成本、容量、速度和功耗因素，选择sdram作为数字图像处理系统的内存。
The controller is used to translate requests coming from host port because DDR2 SDRAM could not execute these com- mands directly.
DDR2内存不能直接识别主端口的请求命令，必须经由内存控制器处理后才能执行。
The controller is used to translate requests coming from host port because DDR2 SDRAM could not execute these com- mands directly.
DDR2内存不能直接识别主端口的请求命令，必须经由内存控制器处理后才能执行。
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