At sometime, just one scan chain or some of the scan chains are active. Average power is reduced.
在某些时刻，仅有一个或者一部分扫描链是活跃的，从而电路的平均功耗和总功耗降低。
Processing time is further decreased by creating multiple scan chains and applying them to multiple pins of the device under test (DUT).
通过产生多个扫描链并将其施加于被测器件(DUT)的多个管脚，可以进一步减少处理时间。
In detail, the inventive methodology is based on the use of scan chains being implemented in the integrated circuit for production testing purposes.
具体地，本发明的方法基于实现在集成电路中用于产品测试目的的扫描链的使用。
After using compatible compression of multiple scan chains to pretreat the merged test set, modified distance-marking method is used to compress test data.
先采用多扫描链相容压缩预处理总测试集，接着使用改进的距离标记法压缩测试数据。
The test vectors of some sub-scan chains generate by controllable LFSR when these chains only need to update test vector and do not need to shift out test responses.
当某个子扫描链的测试向量需要更新且又不需要移出其测试响应时，其测试向量由可控LFSR产生。
This paper presents a novel test scheduling solution, unlike previous techniques that take advantage of balanced scan chains of every single core, utilizing the balance of pairwise combined cores.
不同于以往基于单个芯核扫描链平衡的调度技术，本文提出的对平衡调度技术是利用两个芯核配对后扫描链可能比单个芯核扫描链更平衡，获得比单平衡更短的测试时间。
They would be able to scan larger packet chains in the same amount of time, but that in turn would simply expand the window a little bit, creating yet more work for each new option to be processed.
更快的处理器在同样的时间内会扫描更长的包链，但这样也会造成窗口略微增加，这使得对每个需要处理的新选项的工作量增大。
In the project of HDTV channel receiving ASIC, DFT techniques based on scan-chains, STA (Static Timing Analysis) and formal verification has been adopted.
数字高清晰度电视信道接收芯片实现中使用了基于扫描链的可测试设计和静态验证技术。
In the project of HDTV channel receiving ASIC, DFT techniques based on scan-chains, STA (Static Timing Analysis) and formal verification has been adopted.
数字高清晰度电视信道接收芯片实现中使用了基于扫描链的可测试设计和静态验证技术。
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