For a fixed set of test vectors, the overall test time can be minimized using the scan chain constructed with this method.
对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。
For a fixed set of test vectors, the overall test time can be minimized using the scan chain constructed by this method.
对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。
A scan test scheme based on scan chain disabling technique has been proposed, which can effectively reduce test power. However, its test application time is long.
一种基于扫描链阻塞技术的扫描测试结构被提出来，该结构有效地降低了测试功耗，但其测试应用时间较长。
The invention discloses a memorizer test device based on a scan chain and a use method thereof.
本发明公开了一种基于扫描链的存储器测试装置及其使用方法。
For the test application time can be reduced effectively, this paper proposes an approach based on scan chain disabling technique, in view of incompatible test vector compression method.
为进一步降低测试功耗及测试应用时间，提出一种基于扫描链阻塞技术且针对非相容测试向量的压缩方法。
For the test application time can be reduced effectively, this paper proposes an approach based on scan chain disabling technique, in view of incompatible test vector compression method.
为进一步降低测试功耗及测试应用时间，提出一种基于扫描链阻塞技术且针对非相容测试向量的压缩方法。
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