The deputy mayor of the Paris suburb of Levallois-Perret and a close friend of Sarkozy's told RTL radio this thing.
巴黎郊区勒瓦卢瓦-佩雷的副市长和萨科齐的亲密朋友告诉了RTL电台这件事。
Anna-Bell told the German television station RTL: "we wanted to get married and so we just thought: 'Let's go there."'
Anna - Bell告诉德国电视台RTL说：“我们想结婚，于是就想，那就去吧！”
That proves that he is doing well he told RTL radio.
这证实他做得很好，他告诉RTL电台。
RTL hybrid satisfiability solving is the key technique of RTL verification.
RTL混合可满足性求解是RTL验证中的关键技术。
In Europe, he acquired 90% of RTL Group, a huge radio and television company.
在欧洲，他收购了大型广播电视公司RTL集团90%的股份。
The design includes system level design, RTL level design and logic synthesis.
设计工作包括系统级设计、RTL级设计、逻辑综合。
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
Warrants for RTL are analyzed in view of safety and traffic operation efficiency.
从安全和交通效率两个方面研究左转相位的设置。
The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.
寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。
To do this, the optimizer USES the RTL to create fast or more compact code (or both, when possible).
为此，优化器使用RTL创建快速的或紧凑的代码(或者两者兼顾)。
This paper proposes and implements a novel verification and RTL-Level bug locating method for microprocessors.
本文提出并实现了一种新的基于指令分解的微处理器验证与RTL级错误定位方法。
The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).
高层次综合也叫行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。
By comparing the trace of simulator with that of the processor RTL model, design faults can be quickly and accurately located.
模拟器的运行结果与处理器RTL模型的结果进行对比，大大方便了对RTL模型的验证和查错。
RTL(register transfer level) functional verification system for package assembly function in IPOA application is illustrated in this paper.
介绍一种对IPOA应用中的组包功能进行RTL功能验证的系统。
This dissertation focuses on automatic test generation (ATPG) algorithms for very large-scale integrated circuits at register-transfer-level (RTL).
本文主要是对大规模、超大规模集成电路寄存器传输级（RTL）的自动测试产生算法进行研究。
By studying the algorithms of the filters, this dissertation works out RTL implementation architectures of the CIC module, HB module and FIR module.
根据上述讨论的算法，本文设计了抽取滤波器组中CIC模块、HB模块和FIR模块的RTL实现结构。
Transaction level modeling hides unnecessary details. The communication at transaction level is method calls in comparison with signals and pins at RTL.
事务级建模在RTL级之上，忽略了不必要的细节，把模块之间的通信方式从管脚和信号方式抽象为函数调用。
All structural modules are done with RTL models, and the key modules the Matrix Builder module and the Matrix Multiplier module are discussed in detail.
所有结构模块均实现了RTL级建模，并对其中较复杂的矩阵构造单元和矩阵乘法器模块给出了详细的描述。
The three key modules are all presented as RTL level design and module functional simulation. The deinterlacing system's FPGA design is in the last chapter.
本文对于这三个去隔行系统的关键模块都给出了RTL级设计和模块的功能仿真，并在最后一章中给出了去隔行系统的FPGA设计。
This paper constructs the function simulation platform for buffer manager and the whole system, and validates the design on the platform after the RTL design.
在完成该单元的RTL级设计的基础上，进一步构建了该单元及整个系统的功能仿真平台，在该平台上验证了设计的正确性。
Before the appearance of RTL strategy, Postpone logistics strategy, JIT strategy and other logistics strategies have been put widely into the practice of logistics.
在实时物流战略产生之前，已经有延迟物流战略、准时制生产战略等其他物流战略被广泛地运用在企业的物流实践中。
The work of this dissertation is to complete the RTL design and verification of CLB-PVCI bus bridge after studying and analyzing the CLB bus protocol and PVCI protocol.
本论文工作就是在研究和分析CLB总线协议和PVCI协议的基础上，完成CLB - PVCI总线桥的RTL设计和验证。
Lead ASIC frond-end design team to complete Synthesis, STA, Equivelant Check, Post Layout Simulation, DFT, ATE, Power Control. Make sure RTL code is ok for chip implement.
负责带领整个团队实施芯片的综合、静态时序分析、逻辑一致性分析、后仿真、DFT、ATE、功耗控制。从芯片实现的角度对模块的RTL代码和芯片的RTL代码进行把关。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain.
由于寄存器传输级(rtl)行为描述可以精确地确定数字系统的操作，所以寄存器传输级综合成为当前EDA行业的主流设计方法。
The approach can be easily incorporated into existing RTL to gate equivalence checking frameworks and increase the robustness of equivalence checking for arithmetic circuits.
本算法可直接结合到现有的RTL和门级网表的验证流程中，从而提高算术电路的验证能力。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
Speaking with France legend Bixente Lizarazu for radio station RTL, Wenger said despite problems over the terms of Nasri's new contract, he is still confident of sorting out a New Deal.
在法国电台RTL与法国传奇球星利扎拉祖的对话时，尽管纳斯里的新合同还有些问题，但是他依旧有信心解决它。
Speaking with France legend Bixente Lizarazu for radio station RTL, Wenger said despite problems over the terms of Nasri's new contract, he is still confident of sorting out a New Deal.
在法国电台RTL与法国传奇球星利扎拉祖的对话时，尽管纳斯里的新合同还有些问题，但是他依旧有信心解决它。
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