By pulling up the output, the input buffer circuit enjoys improved margin, and is able to reliably signal a low power condition even when both inputs are low.
通过拉动输出，输入缓冲电路享有改进的余地，能够可靠信号，低功耗条件，即便当两个输入都很低。
By pulling up the output, the input buffer circuit enjoys improved margin, and is able to reliably signal a low power condition even when both inputs are low.
通过拉动输出，输入缓冲电路享有改进的余地，能够可靠信号，低功耗条件，即便当两个输入都很低。
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