A yield driven clock skew scheduling algorithm is proposed in presence of process variations.
针对工艺参数变化的情况，提出一种成品率驱动的时钟偏差安排算法。
The error amplifier IP is suitable for low voltage operations and insensitive to process variations.
该误差放大器芯核同时具有适合低电压工作，并对工艺参数变化不敏感的优点。
This thesis analyzed the current researching situation, introduced process variations and the influence to IC devices, interconnect and circuits.
论文分析了当前的研究状况，介绍了集成电路工艺变异的内容及对集成电路器件、互连以及电路性能的影响。
Based on the theory of the probability interpretation algorithm, a statistical model of RLC interconnect delay in the presence of process variations was put forward.
基于概率解释算法的原理，提出了一种考虑工艺波动的RLC互连延时统计模型，该模型使用了对数正态分布函数。
A new method was proposed for the analysis of crosstalk of non-uniform RLC interconnects with stochastic process variations, and a stochastic perturbation model was proposed.
提出一种基于工艺随机扰动的非均匀rlc互连线串扰分析方法；同时建立了互连线随机扰动模型。
A new method was proposed for the analysis of crosstalk of non-uniform RLC interconnects with stochastic process variations, and a stochastic perturbation model was proposed.
提出一种基于工艺随机扰动的非均匀rlc互连线串扰分析方法；同时建立了互连线随机扰动模型。
应用推荐