The natural waking process helps to set "body clock" and makes people build a healthy sleep and wake habit slowly.
自然清醒的过程有助于设定“生物钟”，让人们建立一个健康的睡眠和慢慢醒来的习惯。
There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost.
从消除信号阻塞到进程执行下一个指令之间，必然会有时钟周期间隙，任何在此时间窗口发生的信号都会丢掉。
With animated visual (for example, a spinning clock), the user has a sense that something is happening and is much more willing to wait for the process to complete.
有了动画视觉(例如，旋转时钟)，用户可以意识到将要发生什么，更愿意等待进程完成。
The clock time is the number of "clock ticks" since the process started.
时钟时间是自该进程启动后的“时钟嘀嗒”数。
Try to schedule actions before noon to allow reporters enough time to process material for the five o 'clock news.
试着在中午之前就安排好活动时间表好让记者有充足的时间去组织今晚5点钟的新闻材料。
This is because process execution now needs to be coordinated across the bus, which operates at half the clock frequency of the chip.
这是因为进程执行现在需要跨总线协调，以一半的芯片时钟频率进行处理。
It will also mean treating retirement as a phased process rather than a sudden event marked by a sentimental speech and a carriage clock.
它还意味着把退休当作是阶段性的过程，而不是由伤感的演讲和一个旅行闹钟所记录的突然事件。
These Numbers must be taken with a grain of salt, because they only represent the time the process spent on the CPU, not the real time it took to execute (also known as the wall clock time).
但是不能完全相信这些数值，因为它们仅表示进程耗费在CPU上的时间，而不是其真正的执行时间(也称为时钟时间)。
But the Godson 3c processor will leapfrog current technology by using a 28-nanometer process, although this will only increase its clock speed by about a factor of two, estimates Halfhill.
数值越小越先进，65纳米工艺落后了32纳米工艺两代而龙芯3c处理器将跳跃性的使用28纳米工艺，Halfhill估计这将使得龙芯有两倍的速度提升。
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟信号进行控制，从而为器件与微处理器或DSP轻松接口创造了条件。
In order to accomplish the data process and conversion, the clock generation circuit, 100% modulation signal and 10% signal demodulation circuit are designed.
为了完成数据的处理和交换，分别设计了时钟产生电路、100%调制信号和10%调制信号的解调电路。
Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise.
过程变化的知识对于最优化电路延时，减少时钟倾斜和降低串扰噪声很重要。
The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs.
转换过程和数据采集过程通过CS和串行时钟进行控制，从而为器件与微处理器或DSP接口创造了条件。
A method is proposed to solve interrupting process of real-time clock.
我们提出了用堆栈方式解决实时时钟中断处理的方法。
The method is a fully-digitized process at the sampling clock rate, so that it can be conveniently implemented by FPGA or DSP, whose synchronization precision can reach 1% of the sampling interval.
该方法是一种基于信号采样时钟速率的全数字化处理过程，其同步精度可达到信号采样间隔的1%以上，且便于FPGA或DSP实现。
A yield driven clock skew scheduling algorithm is proposed in presence of process variations.
针对工艺参数变化的情况，提出一种成品率驱动的时钟偏差安排算法。
Note that the Clock screen runs in a separate background process, thus any changes made to the settings are effective only after you exit the UI application.
请注意，在一个单独的时钟屏幕后台进程运行，从而向任何设置的更改是有效的退出后，才在用户界面应用程序。
Systems with two or more clock domains complicate the testing process.
带两个或更多时钟域的系统是测试过程变复杂。
A non-clock delay-ring A/D converter is presented, which is based on standard cell library and not sensitive to process variation.
提出了一种无需外部时钟、可以部分抵消工艺偏差、基于标准单元的延迟环A/D变换器。
This can happen at any number of places, but in the simplest case the OS is called on every tick of a clock, and decides which process should get the CPU for the next tick of the clock.
这个数字可以发生在任何地方，但在最简单的情况下操作系统被称为每滴答的时钟，并决定哪个进程应该得到CPU时钟的滴答。
This paper introduces the process of logic design of digital circuits, and mainly explains the function of asynchronous counter and decoder. The digital clock is an example of this application.
本文介绍了数字电路系统的逻辑设计过程，并且着重阐明异步计数器和译码器的功能，数字钟是这方面应用的一个实例。
In deep submicron era, IC design in physical design has more and more challenge, with the increasing design scale, faster clock frequency and minimizing process dimension.
在深亚微米时代，随着设计规模变大，时钟频率越来越高以及工艺尺寸的减小，IC物理设计面临着诸多困难。
This paper introduced the electronic clock back of the injection mold design process.
本论文介绍了电子钟后盖的注射模设计过程。
The frame of wireless distributed system is provided, and the work process of clock synchronization based on PTP is introduced.
提出了无线分布式测试系统的构架，介绍了PTP协议的时钟同步工作过程。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
The article presents elementary fruit of our research on how screws and clock parts are coated with aluminium by ion-plating process.
本文主要介绍螺钉、螺帽和钟表零件的离子镀渗铝镀膜性能初步研究成果． 文中着重研究了铝镀膜的性能和组织结构。
The body's daily rhythms are governed by the so-called circadian clock. The clock influences not only when we sleep but also when we get hungry and how efficiently our bodies process food.
身体每天的节律受生物钟的调控，生物钟不仅影响睡眠，还会控制机体何时饥饿及如何有效的消化吸收摄入的食物。
The body's daily rhythms are governed by the so-called circadian clock. The clock influences not only when we sleep but also when we get hungry and how efficiently our bodies process food.
身体每天的节律受生物钟的调控，生物钟不仅影响睡眠，还会控制机体何时饥饿及如何有效的消化吸收摄入的食物。
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