Analyzing the basic theory and development of PLL, and studying the design theory and impedance match problem of experimental circuit board.
分析了锁相环的基本原理和实现，并对射频电路设计理论和阻抗匹配问题进行了探究。
Before we can setout to find the optimal configuration for our PLL, we need to first consider how we find any configuration for our PLL.
在我们准备为锁相环找到最优配置之前，首先要考虑如何找到锁相环的所有配置。
Compared with conventional PLL threshold extended demodulator, it features wider capture range, shorter capture time and significant improvement in threshold level.
与常规pll门限扩展解调器相比，它具有捕获范围宽，捕获时间短，门限改善量显著等优点。
It studies the noise mechanism and its impact on loop stability of PLL circuits and obtains some noise reductive measures, which have proved to be better.
研究了噪声的产生机制和对锁相环稳定性的影响，提出了减小噪声对锁相环性能影响的系列措施，实践证明，达到了较好的效果。
In the field of communications, PLL synthesizers playing an increasingly important role.
在通信领域中，锁相环频率合成器起着越来越重要的角色。
In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
为了尽量减少抖动的锁相环，建议，以避免在测试输出的积极信号。
Due to the frequency pulling of FLL, the passband of the filter in PLL can be made very narrow to suppress the noise, and the PLL can lock carrier's phase with high accuracy.
由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。
A new method is presented for analyzing the acquisition behavior of second-order PLL with sinusoidal phase detector in the absence of noise.
本文给出了一种计算无噪声时具有正弦鉴相器的二阶锁相环捕捉特性的新方法，求得了每个差频周期的平均角频率牵引量。
Actually, the bulk of the work in determining an optimal PLL configuration is wrapped up in determining the list of all possible configurations that meet our needs.
实际上，确定PLL最优配置的大部分工作是确定所有的满足我们需求的配置清单。
In this paper the principle and design of a microcomputer-controlled PLL frequency synthesis digit tuning system is discussed.
本文叙述了一个用微机控制的锁相环频率合成数字调谐系统的原理和设计。
This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.
介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理，给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。
Effectively applying the technology of PLL not only enhance and improve the speed and the veracity of measurement, but also can actualize some special controlling effects.
有效地运用锁相同步技术，不仅可以提高测量的速度、改善测量的准确度，还可以实现一些特殊的控制效果。
The design and implementation of quadrature waveform generator are described based on the AT89C52, phase-locked loop(PLL) and switched-capacitor filter(SCF).
描述了基于AT89C52单片机、锁相环和开关电容滤波器的正交信号发生器的设计和实现方法。
In this paper, a new method of PLL lock detector will be presented.
在本文中，我们将展现一个新的锁相环锁定检测方法。
The PLL full synchronization video detector circuit is educed by feature and troubles of quasi-synchronization video detector.
由准同步视频检波的特点及其存在的问题引出锁相环（ PLL）完全同步视频检波电路。
A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper.
针对电流型电荷泵PLL频率综合器芯片，提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。
High stability PLL-modulator and high sensitivity receiving demodulator are introduced.
介绍了高稳定锁相调制和高灵敏度的接收解调。
A computer aid analysis method for PLL of block-linking type facing systematic mathematical models is proposed.
提出了一种面向系统数学模型的模块连接式锁相环路计算机辅助分析方法。
Phase-locked loop (PLL) has been applied in many fields.
锁相环在很多领域都得到了广泛应用。
A digital-analog PLL is the main part of the data separator.
这个数据分离器的主要部分是一个数模混合的锁相环。
When coincidence between horizontal sync and oscillator frequency is detected, the search mode is replaced by a normal PLL operation.
当水平的同步和振动者频率之间的巧合被发现的时候，搜寻模态被正常PLL操作代替。
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。
For the problem of carrier recovery in DS-SS communication, the model of dual PLL is presented, which is designed based on the auto -adapted algorithm.
针对直接序列扩频通信中的载波恢复问题，提出了一种基于自适应算法设计的双pll载波跟踪方法。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
The digital very narrow-bandwidth Phase-Locked Loop(PLL) is designed and realized for the digital range and velocity measurement receiver.
本文正是为数字化测速测距接收机设计并实现全数字化超窄带锁相环。
Some technique problems in fast frequency hopping synthesis are solved by making use of a programmable time division-fractional division PLL.
该合成器采用程控时分复用小数分频锁相技术，解决了快速跳频频率合成中的诸多固难。
Methods The antibody-targeted complex could be prepared by mixing SPA-PLL conjugate, oligodeoxy nucleotide and anti-CD44 antibody based on their optimal mass ratio.
方法将SPA-PLL交联物、CD44抗体和反义寡核苷酸以适宜的质量比混合即可组装成抗体靶向寡核苷酸复合物；
This system works on UHF frequency brand, use PLL circuit. There are 256 frequencies for your option.
本机工作在UHF频率，采用PLL锁相环电路，预设256个可选择使用频率。
This system works on UHF frequency brand, use PLL circuit. There are 256 frequencies for your option.
本机工作在UHF频率，采用PLL锁相环电路，预设256个可选择使用频率。
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