In this paper we propose a de-pipelining algorithm which converts the optimized assembly code of a software-pipelined loop back to a semantically equivalent sequential counterpart.
提出了一种反流水技术，它能够将软件流水后的优化汇编代码反向转换成语义等价的相应代码。
A macro-pipelining parallel algorithm was proposed for the deduced differential equation, which is improved upon the traditional serial algorithm.
针对推导的微分方程，改进串行求解算法，提出一种宏流水并行算法。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
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