• A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described.

    设计了一个用于流水线型模数转换器的低压采样保持电路

    youdao

  • To reduce the power dissipation and chip size of digital calibration circuits of pipelined analog-to-digital converter (ADC), a new statistics-based background calibration technique is presented.

    为了降低流水线模数转换器数字校准电路规模功耗提出一种新的基于信号统计规律的后台数字校准技术

    youdao

  • To reduce the power dissipation and chip size of digital calibration circuits of pipelined analog-to-digital converter (ADC), a new statistics-based background calibration technique is presented.

    为了降低流水线模数转换器数字校准电路规模功耗提出一种新的基于信号统计规律的后台数字校准技术

    youdao

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