Pipeline architecture can be an important tool in managing security issues from XML's transparency.
管道架构在管理XML透明性所带来的问题时是一种重要的工具。
It is a very high speed VLSI Design through the pipeline architecture with power optimization.
该设计采用流水线处理结构，能达到非常快的处理速度，同时进行了功耗优化。
Compilers are constructed in a pipeline architecture made up of several stages that communicate different forms of data (see Figure 2).
编译器是以一种管道架构来构造的，这种架构由几个阶段(stage)组成，每个阶段处理不同格式的数据(见图2)。
XML pipeline architecture is the idea of effective XML data flow as a set of small, well-defined processing stages (largely, transforms).
XML管道架构是将有效的XML数据流当成一系列定义良好、较小的处理阶段(主要是转换)的思想。
This paper introduces the conception of a pseudo-4-stage pipeline architecture and implements it in the controller of a microprocessor.
提出了伪四级流水结构概念，并在一种微处理器控制器中实现运用。
The way adopted pipeline architecture and changed 2-D DCT/IDCT to two 1-D DCT/IDCT based on characteristic of row-column decomposition.
该方案利用DCT的行列分离特性，采用流水线设计技术，将二维DCT/IDCT实现转化为两个一维DCT/IDCT实现。
Compared with the full parallel architecture, the memory cost of the designed processor decreases, thus the speed is higher than that of the SDF pipeline architecture.
该处理器内存资源消耗较并行结构有所减少，运算速度较单独的SDF流水线结构有所提高。
The radix-2 decimation-in-time algorithm based on 16-bit fixed-point operation and pipeline architecture are adopted in the core module IFFT(Inverse Fast Fourier Transform).
核心模块快速傅立叶逆变换（IFFT）采用基于16位定点运算的基-2时间抽取算法和流水线结构。
Pipeline valves in a variety of urban architecture also substantial growth in demand.
城市建筑中各种阀门管道的需求也大幅度增长。
We also improve the stack architecture and use two-stage pipeline stack.
堆栈结构也做了分析和优化，采用了两级流水线堆栈结构。
The architecture of real time image processing as pipeline structure, massive array and linear array processing, as well as the image understanding system structures, are discussed and compared.
讨论和比较了实时图像处理中的流水线、大阵列处理器及线性阵列处理器结构及实时图像理解的总体结构。
It's much easier to implement the scalable FFT processor based on multilevel pipeline processing architecture.
特别是流水线结构使得FFT处理器可以通过对模块级数的控制，很容易的实现不同点数的FFT计算。
In this paper, based on the analysis about the reconfiguration of the DES, 3des and AES, we propose a reconfigurable architecture, which combines reconfiguration technology with pipeline, par.
本文分析了常用对称密码算法DES、3des和AES的可重构性，利用流水线、并行处理和可重构技术，提出了一种可重构体系结构。
The main approaches of improving FFT processing speed include pipeline and parellel architecture.
提高FFT处理速度的主要途径是采用流水线结构和并行运算。
In this process, a unique parallel video processing architecture combined with SIMD and pipeline MISD is proposed. Modules within the coprocessor are designed individually.
该设计提出了一种将常用的并行SIMD结构与流水线MISD结构相结合的新颖并行视频处理体系结构形式。
Combining with features of ASIP architecture, study on application specific low power optimization technology focusing on instruction set (program code), pipeline and storage.
结合ASIP体系结构特征，以应用特征为指导，针对指令集(程序代码)、流水线和存储部件进行了低功耗优化研究。
For architecture level ones, this paper introduces three kinds of optimization methods, which called operation optimization, instruction optimization and pipeline optimization.
在平台级优化方面，给出了操作优化、指令优化以及流水线优化等三种优化方法。
With the modularization design and pipeline technology, this architecture makes more efficient using of hardware resources.
组单元的模块化设计结构与流水线设计技术使得硬件逻辑资源得到更有效的利用。
This paper proposed a packet processing engine architecture called NRS05, that promotes the efficient dynamic thread scheduling for hiding long latency operations and coping with pipeline stalls.
本文介绍了一个专门面向网络协议处理的硬件多线程包处理微引擎NRS05的设计。
Put forward a data processing full pipeline support architecture base on FPGA by mark up the input data processing pipeline and the output data processing pipeline;
通过划分输入处理流水线和输出处理流水线，提出了一种基于FPGA实现的全流水数据处理支持结构；
The design of branch prediction is mainly studied and the integer pipeline of processor based on EPIC architecture is designed and realized in this paper.
本文的重点是研究基于EPIC体系结构处理器指令分支预测和整数流水线的设计与实现。
The design of branch prediction is mainly studied and the integer pipeline of processor based on EPIC architecture is designed and realized in this paper.
本文的重点是研究基于EPIC体系结构处理器指令分支预测和整数流水线的设计与实现。
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