Arbitrary phase clock management devices can produce high-precision dynamic phase of the clock signal.
任意相位时钟管理器可以产生高精度动态相位的时钟信号。
The latest three-phase clock signal control method was used to control the working state of charge pump.
电路采用了预启动和衬底电位选择结构，并利用三相时钟信号方式控制电荷泵的工作状态。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
The clock, called Sleep Smart, measures your sleep cycle, and waits for you to be in your lightest phase of sleep before rousing you.
这个被称为“智能睡眠”的闹钟会测量你的睡眠周期，等你进入最浅的睡眠阶段后再叫醒你。
You program the clock with the latest time at which you want to be wakened, and it then duly wakes you during the last light sleep phase before that.
你给时钟设定了你想要醒来的最晚时间，然后它会在之前的浅睡眠阶段按时叫醒你。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.
差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。
In this paper, a detailed analysis of a phase interpolator for clock recovery is presented.
分析了应用于时钟恢复电路中的相位插值器。
The orientation or phase of a minute hand on a clock is the amount by which the hand has swept around the clock face: a quarter past the hour, half past the hour, etc.
一个钟表的分针的指向或相位就是分针绕表面扫过的量：一刻钟，半小时等等。
The delay circuit is used for both frequency and phase adjustments of the output clock.
延迟电路可通用于输出时钟的频率调整以及相位调整这两方面。
The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
采用新型的GTL总线收发器、时钟相位调节和组合式匹配等技术措施，解决了总线设计的驱动、时序和信号完整性问题。
The communication protocol could solve the issue of identifying the data boundaries and the phase error caused by the accumulated error of clock.
协议能有效解决数据边界识别问题和时钟累积误差造成的相位偏差问题。
This paper discusses the application of clock representation in three phase transformer connections and other fields.
论述了“时钟表示法”在三相变压器联接组别和在其他方面的应用。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
The compensator includes a phase rotator that controls which write clock phase is selected for output.
补偿器包括控制为输出选择哪个写时钟相位的相位旋转器。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
The reference capacitor can charge at a third clock phase, thus the input signal is released from the capacitor dependently from the voltage.
参考电容器可以在第三时钟相位放电，这样输入信号依赖电压从电容器被释放。
A phase comparator compares the phase of the reference clock with that of the output clock and outputs a phase comparison signal.
相位比较器比较基准时钟和输出时钟的相位，并输出相位比较信号。
The synchronization and separation of the data and clock from floppy disk driver are one of phase-lock techniques' use in computer field.
对软磁盘的数据和时钟的同步和分离，只是锁相技术在计算机领域的应用之一。
Application of the technology of sampling in different phase in clock circuit realizes maximum 200m equivalent sampling rate of timing analyzer.
在时钟电路中采用分相采样技术，实现了定时分析最高200m的等效采样速率。
The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.
输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。
With the signal from the master clock, the slave clock is able to recover an accurate local clock signal using a Clock Recovery Phase Locked Loop (PLL).
从时钟利用主时钟发来的时钟信号，通过数字锁相环恢复出本地时钟信号。
The conversion speed is improved through the reduction of the number of the clock phases required for one conversion and the time allocated for one clock phase.
该技术从减少一个转换周期所需的时钟相数目和减少每个时钟相的时间两个方面来优化速度。
The paper introduces a kind of clock recovery system based on phase-locked loop with bi-directly incident phase-comparator.
介绍了一类基于双向输入型鉴相器锁相环技术的时钟恢复系统。
To test for this scenario, rig up an external phase-locked dual-clock source with a knob that intentionally adjusts the phase relationship of the two clocks.
为了测试这个，做一个外部相位锁定的双时钟源，带有两个时钟有意调节相位关系的节点。
To test for this scenario, rig up an external phase-locked dual-clock source with a knob that intentionally adjusts the phase relationship of the two clocks.
为了测试这个，做一个外部相位锁定的双时钟源，带有两个时钟有意调节相位关系的节点。
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