A via hole is formed in the substrate within the spirally patterned conductor layer, the via hole being formed by through silicon via (TSV).
介层洞形成于螺旋图案化导体层内部的基材中，该介层洞通过硅通孔技术制成。
A via hole is formed in the substrate within the spirally patterned conductor layer, the via hole being formed by through silicon via (TSV).
介层洞形成于螺旋图案化导体层内部的基材中，该介层洞通过硅通孔技术制成。
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