The work of the paper provided valuable experience inapplying the new DSP in high-speed real-time parallel signal processing.
本文为新型DSP在高速实时并行信号处理中的使用积累了经验。
TMS320C80 is a digital signal processor of MIMD structure, which provides a solid foundation for real-time parallel signal processing.
TMS320C80是一种MIMD结构的数字信号处理芯片，为实时并行信号处理提供了强有力的保证。
From the result we can see that the design of each function module of the high speed parallel signal processing system is satisfied with the technical demands.
调试结果表明，高速实时并行信号处理系统的各个功能模块的设计达到了工程设计的技术指标要求。
According to the requirement of technical demands and function realizing, a holistic project about high speed parallel signal processing system which is made up of 4 ADSP21160s is designed.
根据系统的技术指标和功能实现的要求，设计出以4片ADSP21160构成的高速实时并行信号处理系统的整体方案。
Qiapter 2 described the characteristic and performance of the high speed digital signal processor, analyzed and researched three kinds of parallel processing system structure based on DSP.
第2章论述了高速数字信号处理器的特点和性能，对基于DSP的三种并行处理体系结构进行了分析研究。
Multiple DSP parallel digital signal processing system is one of most important method for high-speed DSP system, which find wide application in many different spheres.
多信号处理器并行运算是提高数字信号处理系统运行速度的主要方法之一，具有广阔的应用前景。
When the frequency of the input signal is high enough, parallel processing or equivalent sampling is used.
当输入信号的频率足够高时，一般采用并行处理技术或等效采样技术。
This paper presents a method of the I2S standard audio data and ITU-R 656 format digital video signal processing through synchronous serial port and parallel peripheral interface in DSP.
介绍了一种采用DSP的同步串口和并行外设接口，对I2S标准音频数据和ITU - R 656格式数字视频信号进行处理的方法。
With its strong parallel processing ability and signal processing capacity, the C64 series chips of ti corporation is an ideal platform to run H. 264 CODEC.
TI公司生产的C64系列芯片具有很强的并行处理能力和信号处理功能，是实现H。264编解码的理想平台。
With its strong parallel processing ability and signal processing capacity, the C64 series chips of ti corporation is an ideal platform to run H. 263 CODEC.
TI公司生产的C64系列芯片具有很强的并行处理能力和信号处理功能，是实现H。263编解码的理想平台。
In this paper, a signal processing system based on PCI bus is designed and completed, which is made up of four chips of ADSP21060 (SHARC) which the most advanced parallel DSP device.
本论文采用当前国际上较流行的DSP器件ADSP21060 (SHARC)，设计和实现了一个基于PCI总线的四片adsp21060并行信号处理板。
Then based on the digital signal processor DM642 of TI company, the paper introduces its own digital port. The video port is a bidirectional, high-speed and parallel processing port.
其次以TI公司DM642数字信号处理器为基础，介绍了其特有的数字视频口，该视频口是一种双向，高速的并行处理接口。
Based on one key project, a high-speed digital parallel analyzing system is introduced. The flow of operation of the signal processing program in DSP is defined in detail.
基于某重点工程项目，介绍了一种高速数据并行处理系统，并详细说明了DS P中信号处理程序的操作流程。
This paper presents the design and achievement of a new data structure. The data structure is special for radar signal parallel processing based on a general radar signal processing system.
结合一个通用的雷达信号处理机系统，针对并行雷达信号处理的数据主要为矩阵形式的复数数据的特点，讨论了系统中软件的基本数据结构的定义和实现问题。
They have been intensively used in real application, such as parallel computation, signal processing, associative memory, and so on, which has become an attracting and focused topic.
它们被广泛用于平行计算、信号处理、联想记忆等领域，成为实际应用中的热门课题和很多理论研究者关注的焦点。
Test results indicate that this solution leads to much more flexibility and reliability, and the performance of the equipment is also improved thanks to parallel digital signal processing.
测试结果表明，采用并行化的数字信号处理，增强了设备的灵活性和可靠性，并提高了设备的性能。
The detection device realizes the multi-channel parallel processing of detection signals, the signal processing is stable and the response sensitivity is high.
本发明检测装置实现了对检测信号进行多通道并行处理，信号处理稳定，响应灵敏度高。
Then, basing on this platform, a high speed real-time digital signal processing of radar is carried out, making good use of the parallel design of algorithm and a reasonable assignment of tasks.
在此平台的基础上通过对信号处理算法的并行设计，以及对处理任务的合理分配，实现了高速实时雷达信号处理。
FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features.
在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
Management and scheduling of multi-DSPs (Digital Signal Processing) is the basic elements of controller with parallel and reconfigurable architecture.
多dsp的管理与调度是多处理器并行、可重构结构体系控制器的基础。
Through parallel arithmetic research, a high-parallel-efficiency Radar signal digital pulse compression processing system is designed and optimized, and corresponding experiment result is obtained.
在并行算法研究的基础上，设计并优化了一个高并行效率的雷达信号数字脉冲压缩系统，得出了相应的实验结果。
Then an adaptive parallel processing algorithm for digital signal linear prediction can be given.
由此进一步推导可得到数字信号序列参数线性预测的自适应算法。
The processing of signal DSP can not fill with the demand of the flight control system, therefore two chips of TMS320C6713B are used to design the high-speed information processing parallel system.
单片DSP的处理能力无法满足某飞行控制系统的需求，为此采用两片浮点DSP处理器TMS320C6713B构成高速并行信息处理系统。
The processing of signal DSP can not fill with the demand of the flight control system, therefore two chips of TMS320C6713B are used to design the high-speed information processing parallel system.
单片DSP的处理能力无法满足某飞行控制系统的需求，为此采用两片浮点DSP处理器TMS320C6713B构成高速并行信息处理系统。
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