The PARLOG is a parallel logic programming language, having a prospective application future -in Al and parallel processing area.
PARLOG语言是一种适合于并行逻辑程序设计的语言，广泛应用于人工智能及并行处理等领域。
Place that part of the business logic that is to be processed in parallel inside that event handler.
将要以并行方式执行的该部分业务逻辑放在该事件处理程序内部。
Within the process invoke this event handler multiple times and create in this way a dynamic number of parallel instances of this part of the business logic.
在流程内多次调用此事件处理程序，从而以这种方式创建业务逻辑的这一部分的并行实例(其数量不定)。
Structured activities: for managing the overall process flow for sequencing of activities, parallel processing of activities, and adding conditional logic in controlling the process flow.
结构化活动(Structured activity)：用于管理活动序列的整个流程流、活动的并行处理以及在控制流程流时添加条件逻辑。
The Axis2 architecture separates logic and state; this allows the logic to execute in parallel threads.
Axis2体系结构将逻辑与状态分离；这允许在并行线程中执行逻辑。
Business logic might be run in parallel over all or just a subset of the partitions of the data.
业务逻辑可以完全并行运行，或者仅仅是数据分区的一个子集。
Business processes, on the other hand, are useful for all other cases, especially cases where your business logic is a series of steps that you want to execute sequentially or in parallel.
另一方面，业务流程对于所有其他情况非常有用，尤其是您的业务逻辑是需要按顺序或并行执行一系列步骤的情况。
This includes both caching the data close to the application and replicating application logic close to the (partitioned) data for parallel processing.
这既包括缓存数据使其接近应用程序，又包括复制靠近（分区）数据的应用程序逻辑，以实现并行处理。
A real time optical logic processor is presented, that can perform binary logic operations in parallel. Experimental result is given of the system as a half adder.
本文提出了一种能实时完成二进制逻辑运算的光学并行处理系统，并给出了作为半加法器的实验结果。
Parallel discrete event simulation based on TW is an effect method to improve the speed of simulation, it's common implementation structure is distributed logic process structure.
基于时间偏差的并行离散事件模拟是提高模拟速度的有效手段，其通用系统实现结构是分布式逻辑进程模拟结构。
Granularity control is a main problem of parallel execution of logic programs.
粒度控制是逻辑程序并行执行的重要问题之一。
Applying fuzzy logic control technology to design fuzzy logic torque control strategy of the parallel hybrid electric vehicle.
利用模糊逻辑控制技术，设计了并联混合动力汽车的模糊逻辑扭矩控制策略。
It is put forward in the paper that a new structure is called floating-point accelerating logic with two-way parallel shift chain (TPSC).
本文就浮点加速逻辑提出双向并行移位链式结构，并给出了该结构的逻辑实现方法。
This paper describes the current state of research on parallelism of logic programs and the ways of parallel execution of logic programs.
本文概述了逻辑程序并行性研究的状况和逻辑程序的并行处理方式。
This system is made up of image capture unit, 3 parallel neural network recognition units, mobile characteristics calculation unit, syncretism logic, and corresponding software.
该系统由图像捕获单元，3个并行工作的神经网络识别单元、运动特征计算单元、融合逻辑和相应的软件构成。
With the rapid growth of complexity of VLSI, more and more logic simulation has adopted parallel discrete event simulation.
随着大规模集成电路的复杂性日益增加，逻辑模拟开始采用并行离散事件模拟技术。
This paper presents the principle and the features of a new spatial amplitude encoding pattern method implementing optical parallel array logic gates.
本文给出了执行光学并行阵列逻辑的一种新的空间振幅编码图形法的原理和特性。
By make a programmed of software on the platform, in order to show the parallel interface logic by using computer graphic technology. Also make it available for adjusting and research.
我们通过平台上的软件编程来利用计算机图形图像技术使并行接口的逻辑功能以图形图象的形式显示出来。
It proposes using parallel difference filters to suppress backgrounds, using logic and method to eliminate noise and using recursive method to cumulate the target tracks.
提出用并行差分滤波器去除背景，用逻辑与剔除噪声，用递归方法累积目标轨迹的算法。
By make a programmed of software on the platform, in order to show the parallel interface logic by using computer graphic technology.
我们通过平台上的软件编程来利用计算机图形图像技术使并行接口的逻辑功能以图形图象的形式显示出来。
The router arithmetic of the parallel processor is complex. The circuit has long latency and the logic has the huge size.
并行处理器互连网络的路由算法异常复杂，电路延迟长，逻辑规模巨大，是制约高性能并行处理器提高频率、降低功耗的瓶颈。
This paper presents a distributed logic control strategy for UPS parallel operation.
提出了一种基于平均电流的UPS分散逻辑并联控制方案。
Seven kinds of fundamental fuzzy logic operations in parallel can be all optically realized with the proposed system in this paper. The experimental results are also given.
本系统可全光学并行实现模糊逻辑中的七种基本逻辑运算，并给出了实验结果。
It maps a 2-d logic space onto physical parallel memory modules.
该存储系统完成了二维逻辑空间到物理空间上并行存储器模块的映射。
This paper presents a multiple fault test simulator for sequential logic circuit. The simulator is implemented in serial-parallel to save memory.
本文给出一个时序逻辑电路的多故障测试模拟程序。
To stress the application of Karaugh map on designing of coding circuits in parallel-comparator ADC in terms of the design of combinational logic circuits.
根据组合逻辑电路的设计方法，突出用卡诺图化简逻辑表达式在并联比较型A/D转换器编码电路设计中的应用。
Modern control theory, variable structure control theory and fuzzy logic control theory are applied to contrive two schemes to control Parallel triple inverted-pendulum system.
文中应用现代控制理论、滑模变结构控制理论和模糊控制理论设计了两种三并联耦合倒立摆系统的控制方案。
Parallel computer is a computer with multiple logic or arithmetic units enabling it to perform parallel operations or parallel processing.
并行计算机是一种具有多个运算器，能作并行操作或并行处理的计算机。
Majority logic decoding is one of the simplest high speed decoding techniques to implement, and can completely be done in parallel. Thus, it is suitable to ultra high speed computer systems.
择多逻辑译码是实现最简单的一种译码方法，具有很高的译码速度且便于并行处理，因此，是一种适合于高速计算机应用的译码技术。
Majority logic decoding is one of the simplest high speed decoding techniques to implement, and can completely be done in parallel. Thus, it is suitable to ultra high speed computer systems.
择多逻辑译码是实现最简单的一种译码方法，具有很高的译码速度且便于并行处理，因此，是一种适合于高速计算机应用的译码技术。
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