Three outputs of the system not only can realize the parallel encryption of three or more images, but also increase the more encryption efficiency of the algorithm.
系统三维输出的同时利用，可实现三个或多幅图像的并行加密，提高了算法的加密效率。
Finally, the parallel interface in EPP mode is designed and the whole data encryption system designing between FPGA and PC is given to carry out the verification of data encryption results.
论文的最后设计了EPP模式的并行通信接口，实现了pc机与FPGA之间数据加密系统的调试验证。
Finally, the parallel interface in EPP mode is designed and the whole data encryption system designing between FPGA and PC is given to carry out the verification of data encryption results.
论文的最后设计了EPP模式的并行通信接口，实现了pc机与FPGA之间数据加密系统的调试验证。
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