The parallel decoding method of a parallel concatenation of multiple codes is well known.
多维并行级联码的译码普遍采用并行译码方法。
Though it is simpler than the parallel decoding method in calculation, it gives the same performance as the parallel decoding method.
串行译码方法不仅计算简单，而且所达到的性能与并行译码方法相近。
The proposed algorithm is applicable to the parallel decoding structure and can improve the decoding speed meanwhile keeping the decoding performance unchanged.
该算法适合于并行的译码结构，能够在保持译码性能不变的同时，加快译码速度。
Besides increasing the processing frequency clock of the chips utilized, parallel decoding structure and the related implementation scheme need investigations as well.
除了可以通过提高芯片工作频率来提高译码吞吐率，还需要研究并行译码结构及其实现方案。
Besides increasing the processing frequency clock of the chips utilized, parallel decoding structure and the related implementation scheme need investigations as well.
除了可以通过提高芯片工作频率来提高译码吞吐率，还需要研究并行译码结构及其实现方案。
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