The parallel decoding method of a parallel concatenation of multiple codes is well known.
多维并行级联码的译码普遍采用并行译码方法。
Though it is simpler than the parallel decoding method in calculation, it gives the same performance as the parallel decoding method.
串行译码方法不仅计算简单，而且所达到的性能与并行译码方法相近。
The proposed algorithm is applicable to the parallel decoding structure and can improve the decoding speed meanwhile keeping the decoding performance unchanged.
该算法适合于并行的译码结构，能够在保持译码性能不变的同时，加快译码速度。
Besides increasing the processing frequency clock of the chips utilized, parallel decoding structure and the related implementation scheme need investigations as well.
除了可以通过提高芯片工作频率来提高译码吞吐率，还需要研究并行译码结构及其实现方案。
HP-TBTC can be implemented in parallel to obtain much higher encoding and decoding speed at the cost of more hardware resource.
虽然HP - TBTC结构是以牺牲一定的硬件资源为代价换取编译码的并行处理，但它可以成倍地提高编译码处理速度。
As a result of using the iterative decoding algorithm, which is a parallel algorithm, it can improve the decoding speed and reduce the complexity of decoding.
由于采用迭代译码算法，而且是并行算法，因此能提高译码速度，降低译码的复杂度。
According to the structure of Quasi-Cyclic LDPC code, we can make a trade-off between hardware complexity and decoding throughput by applying semi-parallel architecture.
利用准循环ldpc码的结构特点，使用半并行结构的译码器可以实现复杂度和译码速率的有效折中。
Majority logic decoding is one of the simplest high speed decoding techniques to implement, and can completely be done in parallel. Thus, it is suitable to ultra high speed computer systems.
择多逻辑译码是实现最简单的一种译码方法，具有很高的译码速度且便于并行处理，因此，是一种适合于高速计算机应用的译码技术。
Multi stage parallel connecting weighted resistor decoding network has the properties of simple structure and easy analysis.
多级并接型权电阻解码网络结构简单，分析方便。
The series-parallel hybrid add-compare-select units can reduce the resource occupation and decoding delay of the PLVA decoding, and improve the decoding speed.
串并联混合的加比选单元，可以降低PLVA译码的资源占用及译码时延，提高译码速率。
The parallel concatenated block code has been shown to yield remarkable performance close to theoretical limits, yet admitting a relatively simple iterative decoding technique.
并行级联分组码也已经显示出接近香农理论极限的卓越性能，而其译码采用的也是一种相对简单的迭代译码技术。
The parallel concatenated block code has been shown to yield remarkable performance close to theoretical limits, yet admitting a relatively simple iterative decoding technique.
并行级联分组码也已经显示出接近香农理论极限的卓越性能，而其译码采用的也是一种相对简单的迭代译码技术。
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