Based on the structure of quasi-cyclic LDPC codes, a synchro partially parallel decoder is proposed in this paper.
该文根据准循环ldpc码的结构特点，提出了一种同步部分并行结构的译码器。
The method of designing a parameter configurable and multi-bit parallel BCH decoder is studied in this paper.
本文对可配置参数的多位并行bch译码器的设计方法进行了研究。
Each scan group is selected in turn by decoder so that storage elements in each scan group can be controlled and observed in parallel.
该结构采用译码的方式依次选通每个扫描小组，使得扫描小组中的存储元件并行地控制和观测。
The decoder employs the Normalized MSA algorithm, and Partially Parallel structure for LDPC code in CMMB standard.
本译码器采用改进的最小和译码算法及符合CMMB标准要求的部分并行译码器结构。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
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