• We speak of the brain's processing speed, its storage capacity, its parallel circuits, inputs and outputs.

    这里指的是人脑的处理速率、容量、并行运作、输入输出等。

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  • The probability of success for parallel circuits failure mode is very much better than that of static network mode.

    这种并联失效的模式使抄表成功概率数倍于静态组网方式。

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  • With two parallel circuits on arc powered supply, it settles the welding current unicity, stabilizes forerunner arc and ensures enough welding time.

    电弧供电采用了两种并联电路,解决了焊接电流的单一性,提供了稳定的先导电弧,保证了足够的焊接时间。

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  • Meanwhile skewed slots in rotator, changing the number of parallel circuits of stator windings and optimization of ventilation circuit and shaft structure are also used.

    斜槽;改变定子绕组的并联路数,优化通风风路,优化轴承结构等措施。

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  • Based on phase component model of transmission line, a method to calculate inter-line fault occurred in parallel circuits on same tower is proposed by use of phase component method.

    基于输电线路的相分量模型,提出了利用相分量法对同杆并架线路上的跨线故障进行计算的方法。

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  • By comparing with the present parallel circuits, there are some advantages, less coding states and simpler combinational network, in the circuit proposed. Therefore, it is a valuable circuit model.

    和目前的并接电路相比较,它具有更少的编码状态和更简的组合网络,因此,这是一种有价值的电路。

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  • The article analyzes the frequency characteristics of RC series parallel circuits and the symmetrical circuits, through studying the effectiveness of the positive-negative feedback to the amplifier.

    从正、负反馈对放大器性能影响出发,分析RC串、并联电路及其对偶电路的频率特性。

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  • MIT's Rahul Sarpeshkar is now applying architectural principles from these ultra-energy-efficient cells to the design of low-power, highly parallel, hybrid analog-digital electronic circuits.

    目前,麻省理工学院教授拉胡尔·萨派斯卡正利用这些超能效细胞的构造原则,设计低能耗、高度并行、模数混合的电路。

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  • Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.

    与传统并行数据恢复电路相比,该电路不需要本地参考时钟,并且恢复出的并行数据是位同步的。

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  • Circuits that are in parallel with others almost always mean that some channels get little coolant.

    彼此平行的电路总意味着一些通道得到的冷却剂较少。

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  • This paper describes a New analysis method for active Floating Inductances, an active Floating Inductance can be formed by connecting in parallel two sub - circuits.

    本文叙述实现有源浮地电感的一个新的分析方法,新的有源浮地电感用两个子电路并联构成。

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  • Different ways of earthing, such as one-point earthing, multi-point earthing, series earthing, and parallel earthing should be employed in accordance with diverse circuits.

    一点接地,多点接地,串联接地,并联接地等。电路不同而采用不同的接地方法。

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  • It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.

    它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路,以及串行和并行系统接口端口。

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  • The multi-parallel- magnification circuits and the band-pass filter can well restrain random interfering noise, especially generated by test run vibration.

    适配电路中的多级并联放大电路、带通滤波器对试车过程中的随机干扰信号,尤其是振动引起的噪声具有很强的抑制作用。

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  • To stress the application of Karaugh map on designing of coding circuits in parallel-comparator ADC in terms of the design of combinational logic circuits.

    根据组合逻辑电路的设计方法,突出用卡诺图化简逻辑表达式在并联比较型A/D转换器编码电路设计中的应用。

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  • The parallel test generation technology is an important method to resolve the difficult problem of test on massive circuits.

    并行测试技术是解决当今大规模电路测试难题的一个重要手段。

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  • The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.

    该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路,以及串行和并行系统接口。

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  • The parallel topological analysis for circuits is presented in this paper.

    提出了电路的并行拓扑分析法。

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  • This thesis gets expressions to Q of two LC parallel resonance circuits which are different from each other in form from the definition of Q, and demonstrates that two expressions are the same.

    从品质因数的定义推导出两种形式不同的LC并联谐振回路的Q值表达式,并证明二者的统一性。

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  • Including the construction of main control circuits, synchronization improvements and parallel drivers.

    主要涉及核心控制电路的构成、同步化的改进及驱动电路的并联使用。

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  • Including the construction of main control circuits, synchronization improvements and parallel drivers.

    主要涉及核心控制电路的构成、同步化的改进及驱动电路的并联使用。

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