The first layer is input layer consisting of a group of processing units which are responsible for acceptance of data imported to the network.
第一层即输入层，包含一组处理单元，负责接受向网络输入的数据。
The proposed architecture contains some data processing units and configurable accelerators and on-chip network connecting the heterogeneous cores.
结构中包含数据处理单元、可配置加速部件以及连接各个核的片上网络。
The proposed architecture contains some data processing units and configurable accelerators and on-chip network connecting the heterogeneous cores.
结构中包含数据处理单元、可配置加速部件以及连接各个核的片上网络。
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